About the processor components
These are Code Translation (CT) components, which match functional behavior with what you can observe from software. However, they sacrifice accuracy in timing to achieve fast simulation speeds.
CT processor components translate instructions on the fly and cache the translation to enable fast execution of code. They also use efficient PV bus models to enable fast access to memory and devices.
The CT processor components implement most of the processor features but differ in certain key ways to permit the models to run faster:
- Timing is approximate.
- Selected processor models implement caches, including smartcache, although all processor models implement cache control registers.
- They do not implement write buffers.
- They do not implement micro-architectural features, such as MicroTLB or branch cache.
- Device-accurate modeling of multiple TLBs is off by default.
- They use a simplified view of the external buses.
- Except for the Cortex-A9 and Cortex-A5 processors, there is a single memory access port combining instruction, data, DMA and peripheral access.
- The Cortex-A9 and Cortex-A5 models have two memory access ports, but use only one.
- Processors that support Jazelle only have trivial implementations.
- Cluster models do not simulate all cores at the same time: they run through each core in turn, executing a number of instructions on each core. There can be a bias in the order in which cores run after a restart (for example, core 0 always runs first), so the simulation might hit breakpoints on the favored core more often.
All model Performance Monitor Unit (PMU) registers allow software to program the PMU without aborting. Models implement the cycle count (CCNT) but not the programmable timers. Software can program registers of the PMU but the count value returned is not valid.
For information about the hardware, see the technical reference manuals.