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ARMAEMv8AMPCT component

This section describes the ARM AEMv8-A (MP) CPU component.

ARMAEMv8AMPCT - parameters

This section describes the ARM AEM v8-A (MP) CPU component parameters.

Table 3-1 ARMAEMv8AMPCT parameters

Name Type Default value Description
ADFSR-AIFSR-implemented bool 0x0 ADFSR and AIFSR are implemented
AIDR int 0x0 Value of AIDR_EL1 register.
BPIMVA_causes_translation_lookup bool 0x0 Do a translation when BPIMVA instruction is executed (which may cause a translation fault).
BROADCASTCACHEMAINT bool 0x1 Enable broadcasting of cache maintenance operations to downstream caches. The broadcastcachemaint signal will override this value if used.
BROADCASTINNER bool 0x1 Enable broadcasting of Inner Shareable transactions. The broadcastinner signal will override this value if used.
BROADCASTOUTER bool 0x1 Enable broadcasting of Outer Shareable transactions. The broadcastouter signal will override this value if used.
CCSIDR-L1D_override int 0x0 If nonzero, override the value presented in CCSIDR for L1D (this is cosmetic and does not affect cache behaviour).
CCSIDR-L1I_override int 0x0 If nonzero, override the value presented in CCSIDR for L1I (this is cosmetic and does not affect cache behaviour).
CCSIDR-L2_override int 0x0 If nonzero, override the value presented in CCSIDR for L2 (this is cosmetic and does not affect cache behaviour).
CCSIDR-L3_override int 0x0 If nonzero, allow L3 selection in CSSELR and present this value in CCSIDR (this is cosmetic and does not affect cache behaviour).
CLUSTER_ID int 0x0 Processor cluster ID value
CTIPIDR int 0x0 If non-zero, override the CTI Peripheral Identification Register
CTR-L1Ip-override int 0x0 If non-zero, override the L1Ip bits in CTR/CTR_EL0 system register. This does not change the behaviour of the cache, only what is present in the CTR register.
DBGBCR_BT_applies_RES0_before_valid_check bool 0x1 If true, RES0 behaviour is applied to DBGBCR(_EL1).BT before checking for reserved values for this field.
DBGPIDR int 0x0 If non-zero, override the Debug Peripheral Identification Register
DBGROMADDR int 0x0 Initialization value of DBGDRAR register. Bits[47:12] of this register specify the ROM table physical address.
DBGROMADDRV bool 0x0 If true, set bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid
ERXMISC0_mask int 0x0 Write Mask for ERXMISC0 RAS Register
GICDISABLE bool 0x1 Disable the new style GICv3 CPU interface in each core model. Should be left enabled unless the platform contains a GICv3 distributor.
MIDR int 0x410fd0f0 Value of MIDR_EL1 register.
NUM_CORES int 0x1 Number of cores implemented.
PA_SIZE int 0x28 Physical address range supported. For ARMv8.0 and ARMv8.1 this is limited to 48 bits.
PERIPHBASE int 0x13080000 Base address of peripheral memory space
PMUPIDR int 0x0 If non-zero, override the PMU Peripheral Identification Register
abort_execution_from_device_memory bool 0x0 Execution from device memory generates a prefetch abort.
advsimd_overread bool 0x0 AdvSIMD element load operations access all bytes of a 16-byte aligned window, even in Device memory
align_pc_on_illegal_exception_return_to_aarch32 bool 0x1 Align PC when performing an illegal exception return from AArch64 to AArch32.
apsr_read_restrict bool 0x0 At EL0, unknown bits of APSR are RAZ.
auxilliary_feature_register0 int 0x0 Value of AFR0 ID register.
branch-predictor-clear-policy int 0x2 Set branch prediction policy as defined for MMFR1[31:28]. This does not change the behaviour of the branch predictor, only what is reported in MMFR1.BPred.
branch-predictor-supported-ops int 0x1 Set branch prediction policy as defined for MMFR3[11:8]. This does not change the behaviour of the branch predictor, only what is reported in MMFR3.BPMaint.
cache-log2linelen int 0x6 Log2 of the cache line length in bytes.
cache_maintenance_hits_watchpoints bool 0x0 DCIMVA operations executed in AArch32 modes hit watchpoints.
check_memory_attributes bool 0x1 Detect and report TLB use of conflicting memory attributes for views of the same physical address
clear_reg_top_eret int 0x1 Behaviour of the upper 32-bits of the Xn registers when changing between AArch32 state and AArch64 state. 0, upper 32-bits preserved for all registers. 1, upper 32-bits set to 0 for all accessible registers. 2, upper 32-bits set to 0 for a random selection of accessible registers.
cpacr_trcdis_behaviour int 0x2 Behaviour of CPACR.TRCDIS/NSACR.NSTRCDIS when there is no CP14 ETM interface. 0, RAZ/WI. 2, implemented.
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dbgitr_buffer_size int 0x0 Number of instructions which can be bufferred before EDSCR.ITE is cleared
dcache-hit_latency int 0x0 L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when dcache-state_modelled=true.
dcache-maintenance_latency int 0x0 L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
dcache-miss_latency int 0x0 L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when dcache-state_modelled=true.
dcache-prefetch_enabled bool 0x0 Enable simulation of data cache prefetching. This is only used when dcache-state_modelled=true
dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access (of size dcache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when dcache-state_modelled=true.
dcache-read_bus_width_in_bytes int 0x8 L1 D-Cache read bus width in bytes used to calculate per-access timing annotations
dcache-read_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when dcache-state_modelled=true.
dcache-size int 0x8000 L1 D-Cache size in bytes.
dcache-snoop_data_transfer_latency int 0x0 L1 D-Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-ways int 0x2 L1 D-Cache number of ways (sets are implicit from size).
dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access (of size dcache-write_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-write_latency is set. This is only used when dcache-state_modelled=true.
dcache-write_bus_width_in_bytes int 0x8 L1 D-Cache write bus width in bytes used to calculate per-access timing annotations
dcache-write_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when dcache-state_modelled=true.
dcimva_requires_s2_write_permissions bool 0x0 Data-cache invalidate by MVA operations require stage 2 write permission (virtualised AArch32 guest).
debug_rom_is_flat bool 0x0 If true, present a debug ROM table recommended by ARMv8 Debug Architecture. Otherwise, use nested ROM tables.
delay_serror int 0x0 Add a propagation delay of serror signal into the core
dic-spi_count int 0x40 Number of shared peripheral interrupts implemented
el0_can_access_imp_def_functionality bool 0x0 If not made UNDEF by imp_def_functionality_behaviour, EL0 can access IMPLEMENTATION DEFINED registers and system instructions.
el0_el1_only_non_secure bool 0x0 Secure/non-secure state if EL2 and EL3 are not implemented. 0, secure. 1, non-secure.
enable_tlb_contig_check bool 0x0 Perform extra pagetable walks to check translation table entries that have the contiguous hint bit set.
error_record_feature_register string "" RAS feature register value. JSON schema for the parameter value is: {"ED":0x0,"UI":0x0,"FI":0x0,"UE":0x0,"CFI":0x0,"CEC":0x0,"RP":0x0,"DUI":0x0}. Where ED,UI,FI, and UE have valid values betwn 0x0 - 0x3. CFI and DUI have valid values 0x0, 0x2 and 0x3. CEC has valid values 0x0,0x2 or 0x4. RP has valid value 0x0 or 0x1
exception_catch_type int 0x0 Type of exception catch (ARMv8.0 - ARMv8.1 only). 0, exception trapping. 1, non-exception trapping, higher priority than step. 2, non-exception-trapping, lower priority than step.
exclusive_monitor_clear_on_store_from_same_master bool 0x1 Exclusive monitors in the cluster will be cleared by a store by the same master to the monitored address.
exclusive_monitor_clear_on_strex_address_mismatch bool 0x1 Exclusive monitors in the cluster will be cleared when a strex fails because the address does not match.
exclusive_monitor_clear_on_strex_success bool 0x1 Exclusive monitors in the cluster will be cleared when a strex succeeds.
exercise_stxr_fail bool 0x0 Reject a pseudo-random majority of exclusive store instructions
ext_abort_device_read_is_sync bool 0x1 Synchronous reporting of device read external aborts
ext_abort_device_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_device_write_is_sync bool 0x0 Synchronous reporting of device write external aborts
ext_abort_device_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_fill_data int -0x202020303020203 Returned data, if external aborts are asynchronous
ext_abort_normal_cacheable_read_is_sync bool 0x1 Synchronous reporting of normal cacheable-read external aborts
ext_abort_normal_cacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_cacheable_write_is_sync bool 0x0 Synchronous reporting of normal cacheable write external aborts
ext_abort_normal_cacheable_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_noncacheable_read_is_sync bool 0x1 Synchronous reporting of normal noncacheable-read external aborts
ext_abort_normal_noncacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_normal_noncacheable_write_is_sync bool 0x0 Synchronous reporting of normal noncacheable write external aborts
ext_abort_normal_noncacheable_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_prefetch_is_sync bool 0x1 Behaviour of external aborts generated by instruction fetches. 0, asynchronous abort. 1, synchronous abort.
ext_abort_prefetch_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_so_read_is_sync bool 0x1 Synchronous reporting of strongly ordered read external aborts
ext_abort_so_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_so_write_is_sync bool 0x1 Synchronous reporting of strongly ordered write external aborts
ext_abort_so_write_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_ttw_cacheable_read_is_sync bool 0x1 Synchronous reporting of TTW cacheable read external aborts
ext_abort_ttw_cacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
ext_abort_ttw_noncacheable_read_is_sync bool 0x1 Synchronous reporting of TTW noncacheable read external aborts
ext_abort_ttw_noncacheable_read_ras_type int 0x0 External Aborts are reported as RAS error type specified in this param. Values: 0 = NONE, 1 = UC, 2 = UEU, 3 = UEO , 4 = UER, 5 = CE.
force_align_pc bool 0x0 UNPREDICTABLE branch to non-word-aligned address in ARM state is forced to be aligned
fpcr_short_vector_raz bool 0x0 FPSCR and FPCR fields LEN and STRIDE are hardwired to 0
gic.GICC-offset int 0x2000 Offset from PERIPHBASE for GICC registers.
gic.GICD-offset int 0x1000 Offset from PERIPHBASE for GICD registers. Will be ignored when GICv3 CPU interface is enabled, as distributor is then external to the cluster.
gic.GICH-offset int 0x4000 Offset from PERIPHBASE for GICH registers.
gic.GICH-other-CPU-offset int 0x5000 Offset from PERIPHBASE for GICH registers for accessing other CPUs in the cluster. Set to 0 to disable.
gic.GICV-alias int 0x0 Offset from PERIPHBASE for alias of GICV registers. When gicv2-only, if zero no alias will be created; if gicv2-only=0, the param is deprecated, when zero or unset an alias is created in the place mandated by the architecture (GICV-base+0xF000)
gic.GICV-offset int 0x6000 Offset from PERIPHBASE for GICV registers.
gic.PERIPH-size int 0x8000 Size of registers based at PERIPHBASE that are considered to be owned by the GIC. Any accesses in the range PERIPHBASE to PERIPHBASE+gic.PERIPH-size-1 that do not match GIC registers will be treated as RAZ/WI.
gicv3.A3-affinity-supported bool 0x0 Whether a non-zero value for affinity at level 3 is supported.
gicv3.BPR-min int 0x2 The minimum value for the GICC_BPR register (non-secure version will be 1 + this value).
gicv3.EOI-check-CPUID bool 0x0 Check CPU ID specified for accesses to EOI registers (rather than just ending highest priority active interrupt).
gicv3.EOI-check-ID bool 0x0 Check Interrupt ID specified for accesses to EOI registers (rather than just ending highest priority active interrupt).
gicv3.EOI-deactivate-any-interrupt bool 0x0 Allow an EOI to deactivate interrupts that aren't the highest priority active interrupt (EOI-ignore-out-of-order must be false otherwise this is ignored).
gicv3.EOI-ignore-out-of-order bool 0x1 Ignore EOI writes that cannot end the highest priority active interrupt.
gicv3.FIQEn-RAO bool 0x0 GICC_CTLR.FIQEn is read as one, write insensitive
gicv3.IIDR_base int 0x43b The base value for calculating the GICC_IIDR register value.
gicv3.LR-count int 0x10 The number of implemented list registers.
gicv3.PMHE-RAO-WI bool 0x0 ICC_CTLR_EL*.PHME is read as one, write insensitive
gicv3.PMHE-RAZ-WI bool 0x0 ICC_CTLR_EL*.PHME is read as zero, write insensitive
gicv3.PMHE-release-set-packet bool 0x0 if PHME is enabled, whether a SET packet is released by CPU Intf in Upstream Ack window.
gicv3.SRE-EL2-enable-RAO bool 0x0 When ICC_SRE_EL2.SRE is RAO/WI, makes ICC_SRE_EL2.Enable RAO/WI
gicv3.SRE-EL3-enable-RAO bool 0x0 When ICC_SRE_EL3.SRE is RAO/WI, makes ICC_SRE_EL3.Enable RAO/WI
gicv3.SRE-EL3-set-once bool 0x0 Restrict SRE EL3 to be set only once
gicv3.SRE-enable-action-on-mmap int 0x0 Allowed values are: 0-SRE one allows mmap access. 1-SRE one disables mmap access. 2-SRE one makes mmap access RAZ-WI.
gicv3.STATUSR-implemented bool 0x1 If GICv3 CPU interface is being used, this determines whether the STATUS registers are implemented
gicv3.VBPR-min int 0x2 The minimum value for the GICV_BPR register (non-secure version will be 1 + this value).
gicv3.VFIQEn-RAO bool 0x0 ICH_VMCR_EL2.VFIQEn is read as one, write insensitive
gicv3.cpuintf-mmap-access-level int 0x0 Allowed values are: 0-mmap access is supported for GICC,GICH,GICV registers. 1-mmap access is supported only for GICV registers. 2-mmap access is not supported.
gicv3.dir-trap-support bool 0x1 The cpu supports separate trapping of ICC_DIR_EL1 to EL2
gicv3.gicv2-only bool 0x0 Limit the GIC implementation to GICv2 features only
gicv3.idle-is-ff bool 0x1 For GICC/GICV RPR, when idle, return FF when true, minimum supported priority otherwise
gicv3.ignore-DIR-write-when-EOImode-not-set bool 0x1 Ignore UNPREDICTABLE access to GICC_DIR register.
gicv3.interrupt-bypass-support bool 0x1 Interrupt bypass support, set to false for devices not supporting interrupt bypass
gicv3.local-SEIs bool 0x0 Generate SEI to signal internal issues
gicv3.local-VSEIs bool 0x0 Generate VSEI to signal internal issues
gicv3.physical-ID-bits int 0x10 Number of physical ID bits implemented.
gicv3.priority-bits int 0x5 Number of priority bits implemented.
gicv3.suppress-virtual-enables-comms bool 0x1 In GICv3 only mode, prevents the GIC CPUIF from communicating UpstreamWrite/VirtualEnables to the IRI
gicv3.virtual-ID-bits int 0x10 Number of virtual ID bits implemented.
gicv3.virtual-lpi-support bool 0x1 When GICv3 is supported, indicates a cut down CPUIF interface with no support of VLPI (GICv3 only) when false
gicv3.virtual-priority-bits int 0x5 Number of virtual priority bits implemented.
gicv3.without-DS-support bool 0x0 GICv3 CPU interfaces do not support disabling security in the distributor (GICD_CTLR.DS=1)
hardware_translation_table_update_implemented int 0x1 Implement hardware translation table updates from ARMv8.1. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_16bit_asids bool 0x1 Enable 16-bit ASIDs.
has_16bit_vmids int 0x1 Implement support for 16-bit VMIDs from ARMv8.1. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_16k_granule bool 0x0 Implement the 16k LPAE translation granule.
has_4k_granule bool 0x1 Implement the 4k LPAE translation granule.
has_64k_granule bool 0x1 Implement the 64k LPAE translation granule.
has_aarch32_dbgdidr_etc bool 0x1 DBGDIDR, DBGDRAR, DBGDSAR exist even if EL1 doesn't implement AArch32
has_aarch32_hpd bool 0x0 If true then hierarchical permission disable is supported in AArch32
has_aarch64 bool 0x1 All implemented exception levels can run in AArch64
has_actlr2 bool 0x0 If true ACLTR2 exists and ACTLR2(NS) is aliased to ACTLR_EL1[63:32]
has_arm_v8-1 bool 0x0 Implement the ARMv8.1 Extension.
has_arm_v8-2 bool 0x0 Implement the ARMv8.2 Extension.
has_arm_v8-3 bool 0x0 Implement the ARMv8.3 Extension.
has_ccidx bool 0x0 Implement the ARMv8.3 CCSIDR Extension. Extending the ccsidr number of sets.
has_common_not_private_translations int 0x1 Implement the TTBRn_ELx.CnP (Common not Private) controls from ARMv8.2. Possible values of this parameter are: - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_delayed_dbgreg bool 0x0 Delay the functional effect of external debug register writes until ISB or implicit barrier.
has_delayed_sysreg bool 0x0 Delay the functional effect of system register writes until ISB or implicit barrier.
has_edacr bool 0x1 Implement EDACR register
has_el2 bool 0x1 Implements EL2
has_el3 bool 0x1 Implements EL3
has_exception_trapping_form_of_vector_catch bool 0x1 Implement the exception trapping form of vector catch debug event.
has_far_not_valid bool 0x0 Implements FnV bit in ESR_ELx and xFSR, FAR not valid for synchronous external aborts.
has_fp16 int 0x1 Implement the half-precision floating-point data processing instructions from ARMv8.2. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_hardware_translation_table_update int 0x2 Type of hardware translation table supported (when enabled by hardware_translation_table_update_implemented). 0, not implemented. 1, access bit updates implemented. 2, access bit updates and dirty bit mechanism implemented.
has_itd bool 0x1 Implement the optional IT disable feature.
has_large_64k_ba bool 0x1 If true then it support the large 64KB base address size
has_large_system_ext bool 0x0 Implement the ARMv8 Large System Extensions.
has_large_va int 0x0 Implement support for the extended 52-bit virtual addresses from ARMv8.2. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_ldm_stm_ordering_control int 0x0 Implement the SCTLR_ELx.LSMAOE (Load/Store Multiple Atomicity and Ordering Enable) and SCTLR_ELx,nTLSMD (no Trap Load/Store Multiple to Device) controls from ARMv8.2. Possible values of this parameter are: - 0, feature is not enabled. - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_lrcpc bool 0x0 If true then it support the RCpc feature (ARMv8.3)
has_pc_sample_based_profiling bool 0x1 If true, pc sample-based profiling is enabled.
has_pmu bool 0x1 Implement the optional Performance Monitors Extension.
has_pointer_authentication bool 0x1 Implement pointer authentication (ARMv8.3 only).
has_pstate_pan int 0x1 Implement the PSTATE.PAN (Privileged Access Never) control from ARMv8.1 Possible values of this parameter are: - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_pstate_uao int 0x1 Implement the PSTATE.UAO (User Access Override) control from ARMv8.2. Possible values of this parameter are: - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_ras int 0x0 Implements the ARMv8 RAS Extension. 0 = NO_RAS, 1 = MINIMAL_RAS, 2 = FULL_RAS
has_rounding_doubling_multiply_add_subtract int 0x1 Implement the rounding doubling multiply add and subtract instructions from ARMv8.1 Possible values of this parameter are: - 1, feature is implemented if ARMv8.1 is enabled. - 2, feature is implemented.
has_stage2_xnx int 0x1 Implement the extended XN[1:0] stage 2 control from ARMv8.2. Possible values of this parameter are: - 1, feature is implemented if ARMv8.2 is enabled. - 2, feature is implemented.
has_statistical_profiling bool 0x1 Whether Statistical Based Profiling is implemented
has_tlb_conflict_abort bool 0x0 Detected inconsistent TLB content generate aborts.
has_unsupported_exclusive_fault bool 0x1 Report unsupported exclusive access with Unsupported Exclusive fault status (otherwise use external abort)
has_writebuffer bool 0x0 Implement write accesses buffering before L1 cache. May affect ext_abort behaviour.
hcptr_tta_behaviour int 0x2 Behaviour of HCPTR.TTA when there is no CP14 ETM interface. 0, RAZ/WI. 1, RAO/WI. 2, stateful.
hcr_swio_res1 bool 0x0 Whether HCR.SWIO and/or HCR_EL2.SWIO are RES1.
hsr_uncond_cc bool 0x0 Condition codes reported in HSR as AL if it passes
icache-hit_latency int 0x0 L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when icache-state_modelled=true.
icache-log2linelen int 0x0 If nonzero, Log2 of the instruction cache line length in bytes (valid values in range 4-8). Otherwise the value of cache-log2linelen is used.
icache-maintenance_latency int 0x0 L1 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when icache-state_modelled=true.
icache-miss_latency int 0x0 L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when icache-state_modelled=true.
icache-nprefetch int 0x1 Number of next sequential instruction cache lines to prefetch. This is only used when icache-prefetch_enabled=true.
icache-prefetch_enabled bool 0x0 Enable simulation of instruction cache prefetching. This is only used when icache-state_modelled=true.
icache-prefetch_level int 0x0 0 based cache level at which instructions are pre-fetched. This is only used when icache-prefetch_enabled=true.
icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access (of size icache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when icache-state_modelled=true.
icache-read_bus_width_in_bytes int 0x8 L1 I-Cache read bus width in bytes used to calculate per-access timing annotations
icache-read_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when icache-state_modelled=true.
icache-size int 0x8000 L1 I-Cache size in bytes.
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
icache-ways int 0x2 L1 I-Cache number of ways (sets are implicit from size).
imp_def_functionality_behaviour int 0x0 Behaviour of IMPLEMENTATION DEFINED registers and system instructions. 0, UNDEF. 1, RAZ/WI.
instruction_tlb_size int 0x0 Number of stage1+2 itlb entries (or 0 for unified ITLB+DTLB)
internal_vgic bool 0x1 Instantiate VGIC peripheral in this processor. Should be left enabled unless the platform implements a shared VGIC
is_uniprocessor bool 0x0 Value for the U bit in MPIDR. true disables L1 cache coherency protocols
itd_conditional_instructions_are_32bit bool 0x0 When SCTLR_ELx.ITD=1, an IT instruction plus a T16 instruction are considered a single 32bit conditional instruction.
l2cache-hit_latency int 0x0 L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2cache-state_modelled=true.
l2cache-maintenance_latency int 0x0 L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
l2cache-miss_latency int 0x0 L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2cache-state_modelled=true.
l2cache-read_access_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when l2cache-state_modelled=true.
l2cache-read_bus_width_in_bytes int 0x8 L2 Cache read bus width in bytes used to calculate per-access timing annotations
l2cache-read_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2cache-state_modelled=true.
l2cache-size int 0x80000 L2 Cache size in bytes.
l2cache-snoop_data_transfer_latency int 0x0 L2 Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
l2cache-snoop_issue_latency int 0x0 L2 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when dcache-state_modelled=true.
l2cache-ways int 0x10 L2 Cache number of ways (sets are implicit from size).
l2cache-write_access_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-write_latency is set. This is only used when l2cache-state_modelled=true.
l2cache-write_bus_width_in_bytes int 0x8 L2 Cache write bus width in bytes used to calculate per-access timing annotations
l2cache-write_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2cache-state_modelled=true.
l3cache-hit_latency int 0x0 L3 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l3cache-state_modelled=true.
l3cache-maintenance_latency int 0x0 L3 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
l3cache-miss_latency int 0x0 L3 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l3cache-state_modelled=true.
l3cache-read_access_latency int 0x0 L3 Cache timing annotation latency for read accesses given in ticks per access (of size l3cache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l3cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when l3cache-state_modelled=true.
l3cache-read_bus_width_in_bytes int 0x8 L3 Cache read bus width in bytes used to calculate per-access timing annotations
l3cache-read_latency int 0x0 L3 Cache timing annotation latency for read accesses given in ticks per byte accessed.l3cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l3cache-state_modelled=true.
l3cache-size int 0x0 L3 Cache size in bytes.
l3cache-snoop_data_transfer_latency int 0x0 L3 Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
l3cache-snoop_issue_latency int 0x0 L3 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when dcache-state_modelled=true.
l3cache-ways int 0x10 L3 Cache number of ways (sets are implicit from size).
l3cache-write_access_latency int 0x0 L3 Cache timing annotation latency for write accesses given in ticks per access (of size l3cache-write_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l3cache-write_latency is set. This is only used when l3cache-state_modelled=true.
l3cache-write_bus_width_in_bytes int 0x8 L3 Cache write bus width in bytes used to calculate per-access timing annotations
l3cache-write_latency int 0x0 L3 Cache timing annotation latency for write accesses given in ticks per byte accessed. l3cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l3cache-state_modelled=true.
max_32bit_el int 0x3 Maximum exception level supporting AArch32 modes.
memory.acp.AxCACHE_mask int 0x0 Used with memory.acp.AxCACHE_pattern to define which memory types the ACP port accepts. All transactions which do not satisfy (AxCACHE & mask) == pattern will abort.
memory.acp.AxCACHE_pattern int 0x0 Used with memory.acp.AxCACHE_mask to define which memory types the ACP port accepts. All transactions which do not satisfy (AxCACHE & mask) == pattern will abort.
memory.l2_cache.is_inner_cacheable bool 0x1  
memory.l2_cache.is_inner_shareable bool 0x1  
mixed_endian int 0x1 Implement support for mixed endianness. 0, not supported. 1, supported at all exception levels. 2, supported at EL0 only.
mpidr_layout int 0x0 Layout of MPIDR. 0 AFF0 is CPUID, 1 AFF1 is CPUID
mvbar_reset_is_rvbar bool 0x1 If true then the reset value of MVBAR is RVBAR, if false the reset value is UNKNOWN.
non_secure_vgic_alias_when_ns_only int 0x0 If ! has_el3 and only non-secure side exists, then the normal position of the VGIC is a secure alias. If this parameter is non-zero then in addition a non-secure alias of the VGIC will be placed at this position (aligned to 32 KB).
num_loregion_descriptors int 0x0 Number of Limited Ordering Region descriptors implemented (if ARM v8.1 extensions are implemented)
num_loregions int 0x0 Number of Limited Ordering Regions implemented excluding background region (if ARM v8.1 extensions are implemented)
number_of_error_records int 0x0 Cores Number of Error records supported for RAS
page_based_hardware_attributes int 0x0 Implement the page based hardware attributes from ARMv8.2. This parameter indicates which page table bits are available for hardware, where bits[3:0] correspond to PTE[62:59] and to TCR_ELx.HWUnyy.
pmu-num_counters int 0x8 Number of pmu counters implemented
pmu_has_chain_event bool 0x1 PMU (if present) implements event number 0x1e, CHAIN.
ptw_latency int 0x0 Page table walker latency for TA (Timing Annotation), expressed in simulation ticks
register_reset_data int 0x0 Data used to fill register bits when they become UNKNOWN at reset.
report_iside_cmo_ifsr bool 0x1 fault info for an iside cache maintenance operation is reported in the IFSR
scheduler_mode int 0x0 Control the interleaving of instructions in this processor. 0, default long quantum. 1, low latency mode, short quantum and signal checking. 2, lock-breaking mode, long quantum with additional context switches near load-exclusive instructions.
scr_nET_writeable bool 0x0 Whether SCR.nET is writeable. Writing to it is purely cosmetic (nET behavior not implemented)
scramble_unknowns_at_reset bool 0x1 Will fill in unknown bits in registers at reset with register_reset_data
spsr_el3_is_mapped_to_spsr_mon bool 0x1 Whether SPSR_EL3 is mapped to AArch32 register SPSR_mon
stage12_tlb_size int 0x80 Number of stage1+2 tlb entries.
stage1_tlb_size int 0x0 Number of stage1 only tlb entries.
stage1_walkcache_size int 0x0 Number of stage1 only walk cache entries.
stage2_tlb_size int 0x0 Number of stage2 only tlb entries.
stage2_walkcache_size int 0x0 Number of stage2 only walk cache entries.
statistical_profiling_buffer_alignment int 0x1 Statistical profiling alignment constraint for sample buffer
statistical_profiling_edge_triggered_irq bool 0x1 Statistical profiling uses an edge rather than level triggered interrupt
statistical_profiling_random_interval_is_separate bool 0x0 Statistical profiling random interval gets added to the main timer interval(false) or (true) runs as separate timer
statistical_profiling_recommended_min_sampling int 0x100 Statistical profiling recommended minimum sampling interval
supports_multi_threading bool 0x0 Sets the MPIDR.MT bit. Setting this to true hints the the cluster is multi-threading compatible
take_ccfail_tsc_trap bool 0x0 When take_ccfail_undef=1 this prameter controls whether or not an SMC instruction that is trapped by HCR_EL2.TSC but fails its condition code check generates a trap to EL2.
take_ccfail_undef bool 0x1 UNDEF exception is taken even if condition code check fails
tidcp_traps_el0_undef_imp_def bool 0x1 TIDCP has priority over UNDEF for accesses to IMPLEMENTATION DEFINED functionality from EL0
tlb_latency int 0x0 TLB latency for TA (Timing Annotation), expressed in simulation ticks
trace_has_sysreg_access bool 0x1 ETM trace registers support access via system registers
treat-dcache-invalidate-as-clean-invalidate bool 0x0 Treat data cache invalidate operations as clean and invalidate.
treat_pld_as_nop bool 0x0 If true, treat PLD as NOP.
treat_pli_as_nop bool 0x0 If true, treat PLI as NOP.
treat_wfi_wfe_as_nop bool 0x0 If true, never go into wait state for WFI or WFE instructions.
unification-level int 0x1 Level of Unification Inner Shareable for the cache hierarchy
unification-uniprocessor-level int 0x1 Level of Unification Uniprocessor for the cache hierarchy
unpred_edscr_rw_unknown_bits_read_as_1 bool 0x0 Unknown(x) bits in RW field in EDSCR are read as 1 instead of 0.
unpred_load_single_reg_overlap_with_wb int 0x0 Constrained unpredictable behaviours for single load with writeback(might impact certain load pair instructions) 0 Constraint_WBSUPPRESS, 1 Constraint_UNDEF, 2 Constraint_NOP
unpred_mrsmsr_currentlymapped_undef bool 0x0 UNPREDICTABLE register access (accessible from current mode using different instruction) modeled as NOP when false and UNDEF when true
unpred_mrsmsr_protfailed_undef bool 0x0 UNPREDICTABLE register access (not accessible from current PL and security state) modeled as NOP when false and UNDEF when true
unpred_store_exclusive_base_overlap int 0x0 Constrained unpredictable behaviours for store exclusive when s==n. 0 Constraint_NONE, 1 Constraint_UNDEF, 2 Constraint_NOP
unpred_store_pair_and_single_reg_overlap_with_wb int 0x0 Constrained unpredictable behaviours for pair and single store with writeback(doesn't cover store exclusive) 0 Constraint_NONE, 1 Constraint_UNDEF, 2 Constraint_NOP
unpred_tsize_aborts bool 0x0 Behaviour when TSize is out of range. 0, force into range. 1, translation fault, forces unpred_tsize_pamax_aborts to 1.
unpred_tsize_pamax_aborts bool 0x0 Behaviour when stage 2 TSize exceeds the physical address size (or 40bits, from AArch32). 0, force into range. 1, translation fault. Ignored if unpred_tsize_aborts is 1.
unpredictable_exclusive_abort_memtype int 0x0 Cause MMU abort if exclusive access is not supported in certain memory type (0=exclusives allowed in all memory types, 1=exclusives abort in Device memory types, 2=exclusives abort in any type other than WB inner cacheable)
unpredictable_hvc_behaviour int 0x0 HVC unpredictable behaviour. 0, UNDEF. 1, NOP.
unpredictable_smc_behaviour int 0x0 SMC unpredictable behaviour. 0, UNDEF. 1, NOP.
use_tlb_contig_hint bool 0x0 Translation table entries with the contiguous hint bit set generate large TLB entries.
user_defined_rom_table_debug_memory_map string "" User defined ROM Table debug memory map for ED,CTI,PMU and TRACE. JSON schema for the parameter value is: {"format":"all_addrs_are_absolute_wrt_debugbus","cores": [{"ed":0x0,"cti":0x0,"pmu":0x0,"etm":0x0},{"ed":0x0,"cti":0x0,"pmu":0x0,"etm":0x0},{"ed":0x0,"cti":0x0,"pmu":0x0,"etm":0x0},{"ed":0x0,"cti":0x0,"pmu":0x0,"etm":0x0}]}
walk_cache_latency int 0x0 Walk cache latency for TA (Timing Annotation), expressed in simulation ticks
warn_unpredictable_in_v7 bool 0x1 If true, behaviour which is unpredictable in V7 yet is predictable in V8 will produce a warning
watchpoint-log2secondary_restriction int 0x0 log2 size of secondary restriction of FAR/EDWAR possible values on watchpoint hit for load/store operations.

Table 3-2 ARMAEMv8AMPCT core parameters

The models use the parameters for cores in sequence, from cpu0 onwards. If there are fewer cores than the maximum number, models ignore parameters for uninstantiated cores.

Note

  • The core identifier, n can be in the range 0 to (NUM_CORES-1).
  • The model needs the separate cryptography plug-in to enable the cryptographic instructions.
Name Type Default value Description
cpun.CFGEND bool 0x0 Endianness configuration at reset. 0, little endian. 1, big endian.
cpun.CONFIG64 bool 0x1 Register width configuration at reset. 0, AArch32. 1, AArch64.
cpun.CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
cpun.CRYPTODISABLE bool 0x0 Disable cryptographic features.
cpun.DCZID-log2-block-size int 0x8 Log2 of the block size cleared by DC ZVA instruction (as read from DCZID_EL0).
cpun.MPIDR-override int 0x0 Override of MPIDR value. If nonzero will override the MT, cluster and CPU ID bits in MPIDR.
cpun.RVBAR int 0x0 Value of RVBAR_ELx register.
cpun.SMPnAMP bool 0x1 Enable broadcast messages necessary for correct SMP operation at reset.
cpun.TEINIT bool 0x0 Instruction set state when resetting into AArch32. 0, A32. 1, T32.
cpun.VINITHI bool 0x0 Reset value of SCTLR.V.
cpun.ase-present bool 0x1 Set whether the model has been built with NEON support
cpun.clock_divider int 0x1 Clock divider ratio for asymmetric MP clocking.
cpun.clock_multiplier int 0x1 Clock divider ratio for asymmetric MP clocking.
cpun.crypto_aes int 0x2 AES instructions supported (requires CryptoPlugin to be loaded). 0, not implemented. 1, AES instructions implemented. 2, AES and PMULL instructions implemented.
cpun.crypto_sha1 int 0x1 SHA-1 instructions supported (requires CryptoPlugin to be loaded). 0, not implemented. 1, SHA1 instructions implemented.
cpun.crypto_sha256 int 0x1 SHA-256 instructions supported (requires CryptoPlugin to be loaded). 0, not implemented. 1, SHA256 instructions implemented.
cpun.cti-intack_mask int 0x1 Set bits represent that the corresponding trigger requires software acknowledge via CTIINTACK
cpun.cti-number_of_claim_bits int 0x0 Number of implemented bits in CTICLAIMSET
cpun.cti-number_of_triggers int 0x8 Number of cti event triggers
cpun.enable_crc32 int 0x0 CRC32 instructions supported. 0, not implemented. 1, CRC32 instructions implemented.
cpun.etm-present bool 0x1  
cpun.force-fpsid bool 0x0 Override the FPSID value
cpun.force-fpsid-value int 0x0 Value to override the FPSID value to
cpun.has_hcptr_tase bool 0x1 If false, HCPTR.TASE is RES0
cpun.max_code_cache int 0x4000000 Maximum number of bytes for caching code translations.
cpun.min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpun.number-of-breakpoints int 0x10 Number of breakpoints.
cpun.number-of-context-breakpoints int 0x10 Number of breakpoints that are context aware.
cpun.number-of-watchpoints int 0x10 Number of watchpoints.
cpun.semihosting-A32_HLT int 0xf000 A32 HLT number for semihosting calls.
cpun.semihosting-A64_HLT int 0xf000 A64 HLT number for semihosting calls.
cpun.semihosting-ARM_SVC int 0x123456 A32 SVC number for semihosting calls.
cpun.semihosting-T32_HLT int 0x3c T32 HLT number for semihosting calls.
cpun.semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting calls.
cpun.semihosting-cmd_line string "" Command line available to semihosting calls.
cpun.semihosting-cwd string "" Base directory for semihosting file access.
cpun.semihosting-enable bool 0x1 Enable semihosting SVC/HLT traps.
cpun.semihosting-heap_base int 0x0 Virtual address of heap base.
cpun.semihosting-heap_limit int 0xf000000 Virtual address of top of heap.
cpun.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack.
cpun.semihosting-stack_limit int 0xf000000 Virtual address of stack limit.
cpun.semihosting-stderr_istty bool 0x1 Result for semihost istty call when argument is stderr
cpun.semihosting-stdin_istty bool 0x1 Result for semihost istty call when argument is stdin
cpun.semihosting-stdout_istty bool 0x1 Result for semihost istty call when argument is stdout
cpun.semihosting-use_stderr bool 0x0 Send stderr from the simulated process to host stderr
cpun.unpredictable_WPMASKANDBAS int 0x1 Constrained unpredictable handling of watchpoints when mask and BAS fields specified. 0, IGNOREMASK. 1, IGNOREBAS (default). 2, REPEATBAS8. 3, REPEATBAS.
cpun.vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: ARM recommends going though the implementation's suggested VFP power-up sequence!
cpun.vfp-present bool 0x1 Set whether the model has VFP support
cpun.vfp-traps bool 0x1  

ARMAEMv8AMPCT - ports

This section describes the ports.

Table 3-3 ARMAEMv8AMPCT ports

Name Protocol Type Description
CNTHPIRQ Signal Master Timer signals to SOC.
CNTHVIRQ Signal Master Timer signals to SOC.
CNTPNSIRQ Signal Master Timer signals to SOC.
CNTPSIRQ Signal Master Timer signals to SOC.
CNTVIRQ Signal Master Timer signals to SOC.
acp_s PVBus Slave AXI ACP slave port.
broadcastcachemaint Signal Slave ACE defined pins.
broadcastinner Signal Slave ACE defined pins.
broadcastouter Signal Slave ACE defined pins.
broadcastpersistent Signal Slave CHI defined pins.
cfgend Signal Slave This signal if for EE bit initialisation.
cfgsdisable Signal Slave This signal disables write access to some secure Interrupt Controller registers.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
clusterid Value Slave The port reads the value in CPU ID register field, bits[11:8] of the MPIDR.
cntvalueb CounterInterface Slave Interface to SoC level counter module.
commirq Signal Master Interrupt signal from debug communications channel.
config64 Signal Slave Register width after reset.
cp15sdisable Signal Slave This signal disables write access to some system control processor registers.
cpuporeset Signal Slave  
cryptodisable Signal Slave Disable cryptography extensions after reset.
cti v8EmbeddedCrossTrigger_controlprotocol Master Cross trigger matrix port.
cti0extin Signal Slave  
cti0extout Signal Master  
cti1extin Signal Slave  
cti1extout Signal Master  
cti2extin Signal Slave  
cti2extout Signal Master  
cti3extin Signal Slave  
cti3extout Signal Master  
ctidbgirq Signal Master  
dbgen Signal Slave External debug interface.
dbgnopwrdwn Signal Master Debug no power down request.
dbgpwrdwnack Signal Master Debug power down acknowledge.
dbgpwrdwnreq Signal Slave Debug power down request.
dbgpwrupreq Signal Master Debug power up request.
dev_debug_s PVBus Slave External debug interface.
etm PVBus Master Embedded trace macrocell port.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE.
external_trace_reset Signal Slave  
fiq Signal Slave This signal drives the CPUs fast-interrupt handling.
gicv3_redistributor_s GICv3Comms Slave GICv3 cpu interface ports.
irq Signal Slave This signal drives the CPUs interrupt handling.
irqs Signal Slave This signal drives the CPU interrupts.
l2reset Signal Slave This signal resets timer and interrupt controller.
memorymapped_debug_s PVBus Slave External debug interface.
niden Signal Slave External debug interface.
periphbase Value_64 Slave This port sets the base address of private peripheral region.
pmbirq Signal Master Interrupt signal from the statistical profiling unit.
pmuirq Signal Master Interrupt signal from performance monitoring unit.
presetdbg Signal Slave  
pvbus_m0 PVBus Master The core will generate bus requests on this port.
rei Signal Slave Individual processor RAM Error Interrupt signal input.
reset Signal Slave Raising this signal will put the core into reset mode.
romaddr Value_64 Slave Debug ROM base address.
romaddrv Signal Slave Debug ROM base address valid.
rvbar Value_64 Slave Reset vector base address.
sei Signal Slave Per core System Error physical pins.
smpnamp Signal Master This signals AMP or SMP mode for each core.
spiden Signal Slave External debug interface.
spniden Signal Slave External debug interface.
standbywfe Signal Master This signal indicates if a core is in WFE state.
standbywfi Signal Master This signal indicates if a core is in WFI state.
standbywfil2 Signal Master This signal indicated all cores and L2 are in a power down state
teinit Signal Slave This signal provides default exception handling state.
ticks InstructionCount Master This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
trace_unit_reset Signal Slave  
vcpumntirq Signal Master Interrupt signal for virtual CPU maintenance IRQ.
vfiq Signal Slave Virtual FIQ input. Note that the irq/fiq pins are wired directly to the core if there is no internal VGIC. If there is an internal VGIC then these are ignored.
vinithi Signal Slave This signal controls of the location of the exception vectors at reset.
virq Signal Slave Virtual IRQ input. Note that the irq/fiq pins are wired directly to the core if there is no internal VGIC. If there is an internal VGIC then these are ignored.
virtio_s PVBus Slave The virtio coherent port, hooks directly into the L2 system and becomes coherent (assuming attributes are set correctly).
vsei Signal Slave Processor Virtual System Error Interrupt request.
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