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ARMCortexA12xnCT component

This section describes the ARMCortexA12xnCT component.

ARMCortexA12xnCT - about

This C++ component is a model of r0p0 of a Cortex®-A12 processor containing from one to four cores. The n shows the number of cores.

ARMCortexA12xnCT - ports

This section describes the ports.

Table 3-36 ARMCortexA12xnCT ports

Name Protocol Type Description
acp_s PVBus Slave Advanced eXtensible Interface (AXI) ACP slave port.
broadcastcachemaint Signal Slave Controls issuing of cache maintenance transactions, such as CleanShared, CleanInvalid and MakeInvalid, on the coherent interconnect.a
broadcastinner Signal Slave Controls issuing of coherent transactions targeting the Inner Shareable domain on the coherent interconnect.a
broadcastouter Signal Slave Controls issuing of coherent transactions targeting the Outer Shareable domain on the coherent interconnect.a
cfgend[4] Signal Slave Initialize to BE8 endianness after a reset.
CFGADDRFILTENDNS Value_64 Slave peripheral_m port NS end address, using only bits[39:20].
CFGADDRFILTENDS Value_64 Slave peripheral_m port S end address, using only bits[39:20].
CFGADDRFILTENNS Signal Slave Enable peripheral_m port filtering for NS accesses.
CFGADDRFILTENS Signal Slave Enable peripheral_m port filtering for S accesses.
CFGADDRFILTSTARTNS Value_64 Slave peripheral_m port NS start address, using only bits[39:20].
CFGADDRFILTSTARTS Value_64 Slave peripheral_m port S start address, using only bits[39:20].
clk_in ClockSignal Slave Main processor clock input.
clusterid Value Slave Sets the value in the CLUSTERID field (bits[11:8]) of the MPIDR.
CNTHPIRQ[4] Signal Master Hypervisor physical timer event.
CNTPNSIRQ[4] Signal Master Non-secure physical timer event.
CNTPSIRQ[4] Signal Master Secure physical timer event.
cntvalueb CounterInterface Slave Synchronous counter value. Connect this to the MemoryMappedCounterModule component.
CNTVIRQ[4] Signal Master Virtual timer event.
cpuporeset[4] Signal Slave Power-on reset. Initializes all the processor logic, including the NEON and VFP, Debug, PTM, breakpoint, and watchpoint logic in the processor CLK domain.
cp15sdisable[4] Signal Slave Disable write access to some secure cp15 registers.
event Signal Peer Event input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
fiq[4] Signal Slave Processor FIQ signal input.
irq[4] Signal Slave Processor IRQ signal input.
l2flushreq Signal Slave Request flush of L2 memory system.
l2flushdone Signal Master Flush of L2 memory system complete.
l2reset Signal Slave Reset shared L2 memory system, interrupt controller and timer logic.
peripheral_m PVBus Master Peripheral port of the processor, under control by filter registers.
pmuirq[4] Signal Master Performance Monitoring Unit (PMU) interrupt signal.
presetdbg Signal Slave Initializes the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_m0 PVBus Master AXI bus master channel.
reset[4] Signal Slave Individual processor reset signal.
standbywfe[4] Signal Master Indicates if a processor is in Wait For Event (WFE) state.
standbywfi[4] Signal Master Indicates if a processor is in Wait For Interrupt (WFI) state.
teinit[4] Signal Slave Initialize to take exceptions in T32 state after a reset.
ticks[4] InstructionCount Master Processor instruction count for visualization.
vfiq[4] Signal Slave Processor virtual FIQ signal input.
vinithi[4] Signal Slave Initialize with high vectors enabled after a reset.
virq[4] Signal Slave Processor virtual IRQ signal input.
virtio_s PVBus Slave Virtio coherent port, which hooks into the L2 system and becomes coherent, given correct attributes.

ARMCortexA12xnCT - parameters

This section describes the parameters.

Table 3-37 ARMCortexA12xnCT parameters

Name Type Allowed values Default value Description
CFGADDRFILTENDNS uint64_t 0-0xFFFFF00000 0 peripheral_m port NS end address.
CFGADDRFILTENDS uint64_t 0-0xFFFFF00000 0 peripheral_m port S end address.
CFGADDRFILTENNS bool true, false false peripheral_m port NS address filtering enabled.
CFGADDRFILTENS bool true, false false peripheral_m port S address filtering enabled.
CFGADDRFILTSTARTNS uint64_t 0-0xFFFFF00000 0 peripheral_m port NS start address.
CFGADDRFILTSTARTS uint64_t 0-0xFFFFF00000 0 peripheral_m port S start address.
CLUSTER_ID uint32_t 0-0xF 0 Cluster ID value.
IMINLN bool true, false true Instruction cache minimum line size. false, 32 bytes. true, 64 bytes.
l1_dcache-state_modelled bool true, false false Set whether L1 D-cache has stateful implementation.
l1_icache-state_modelled bool true, false false Set whether L1 I-cache has stateful implementation.
l2_cache-size uint32_t 512KB, 1MB, 2MB, 4MB 0x40000 Set L2 cache size in bytes.
l2_cache-state_modelled bool true, false false Set whether L2 cache has stateful implementation.

Table 3-38 ARMCortexA12xnCT core parameters

Name Type Allowed values Default value Description
ase-presentb bool true, false true Model has NEON™ support.
CFGEND bool true, false false Initialize to BE8 endianness.
CP15SDISABLE bool true, false false Initialize to disable access to some CP15 registers.
cpi_div uint32_t 0x1-0x7FFFFFFF 0x1 Divider for calculating Cycles Per Instruction (CPI).
cpi_mul uint32_t 0x1-0x7FFFFFFF 0x1 Multiplier for calculating CPI.
DBGROMADDR uint32_t 0x0-0xFFFFFFFF 0x12000003 Initializes the CP15 DBGDRAR register. Bits[39:12] of this register specify the ROM table physical address.
DBGROMADDRV bool true, false true If true, this sets bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid.
DBGSELFADDR uint32_t 0x0-0xFFFFFFFF 0x00010003 Initializes the CP15 DBGDSAR register. Bits[39:17] of this register specify the ROM table physical address.
DBGSELFADDRV bool true, false true If true, this sets bits[1:0] of the CP15 DBGDSAR to indicate that the address is valid.
l1_icache-size uint32_t 0x8000-0x10000 0x8000 Size of L1 I-cache.
min_sync_level uint32_t 0x0-0x03 0x0 Controls the minimum syncLevel. 0x0, off = default. 0x1, syncState. 0x2, postInsnIO. 0x3, postInsnAll.
semihosting-ARM_SVC uint32_t 0x0-0xFFFFFF 0x123456 A32 SVC number for semihosting.
semihosting-cmd_line string - "" Command line available to semihosting SVC calls.
semihosting-cwd string - "" Base directory for semihosting file access.
semihosting-enable bool true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-heap_base uint32_t 0x0-0xFFFFFFFF 0 Virtual address of heap base.
semihosting-heap_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base uint32_t 0x0-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 Virtual address of stack limit.
semihosting-Thumb_SVC uint32_t 0x0-0xFF 0xAB T32 SVC number for semihosting.
TEINIT bool true, false false T32 exception enable. The default has exceptions including reset handled in A32 state.
vfp-enable_at_resetc bool true, false false Enable coprocessor access and VFP at reset.
vfp-presentb bool true, false true Model has VFP support.
VINITHI bool true, false false Initialize with high vectors enabled after a reset.

ARMCortexA12xnCT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the integration and test registers.

ARMCortexA12xnCT - caches

This component implements L1 and L2 caches as architecturally defined.

ARMCortexA12xnCT - debug features

The component exports a CADI debug interface.

ARMCortexA12xnCT - debug - registers

All core, VFP, CP14, and CP15 registers are visible in the debugger. All CP14 debug registers are implemented.

ARMCortexA12xnCT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexA12xnCT - debug - memory

The component presents three 4GB views of virtual address space, that is, one in hypervisor, one in secure mode and one in non-secure mode.

ARMCortexA12xnCT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of Linux on an example system.

ARMCortexA12xnCT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • The Broadcast Translation Lookaside Buffer (TLB) or cache operations in this model do not cause other cores in the cluster that are asleep because of Wait For Interrupt (WFI) to wake up.
  • The RR bit in the SCTLR is ignored.
  • The Power Control Register in the system control coprocessor is implemented but writing to it does not change the behavior of the model.
  • When modeling the SCU, coherency operations are represented by a memory write followed by a read to refill from memory, rather than using cache-to-cache transfers.
  • ETM registers are not implemented.
  • TLB bitmap registers are implemented as RAZ/WI.
  • The Cortex-A12 mechanism to read the internal memory used by the Cache and TLB structures through the implementation defined region of the system coprocessor interface is not supported. This includes the RAM Index Register, IL1DATA Registers, DL1DATA Registers, and associated functionality.
a AXI Coherency Extensions (ACE) defined pin.
b The ase-present and vfp-present parameters configure the synthesis options.
vfp present and ase present
NEON and VFPv4-D32 supported.
vfp present and ase not present
VFPv4-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv4-D32 support.
vfp not present and ase not present
Model has neither NEON nor VFPv4-D32 support.
c This is a model-specific behavior with no hardware equivalent.
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