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ARMCortexA35xnCT component

This section describes the ARMCortexA35xnCT component.

ARMCortexA35xnCT - about

This C++ component is a model of r0p0 of an ARMv8-A Cortex®-A35 processor containing from one to four cores. The n shows the number of cores.

ARMCortexA35xnCT - ports

This section describes the ARMCortexA35xnCT ports.

Table 3-20 ARMCortexA35xnCT ports

Name Protocol Type Description
aa64naa32[0-3] Signal Slave Register width state after reset.
acp_s PVBus Slave Bus slave on which the processor receives coherency transactions. It is a Programmer’s View (PV) of the Advanced Extensible Interface (AXI) Accelerator Coherency Port (ACP) slave port.
broadcastinner Signal Slave Enable broadcasting of inner shareable transactions.
broadcastouter Signal Slave Enable broadcasting of outer shareable transactions.
broadcastcachemaint Signal Slave Enable broadcasting of cache maintenance operations to downstream caches.
cfgend[0-3] Signal Slave Configure endianness at reset: set the value of the EE bits in the CP15 SCTLR_EL3 and SCTR_S registers.
cfgsdisable Signal Slave Disables write access to some secure Interrupt Controller registers.
cfgte[0-3] Signal Slave Initialize to take exceptions in T32 state after reset.
clk_in ClockSignal Slave Processor clock input, for determining the rate of instruction execution relative to other system components.
clrexmonack Signal Master Acknowledge handshake signal for the clrexmonreq signal.
clrexmonreq Signal Slave Signals the clearing of an external global exclusive monitor.
clusterid Value Slave The port reads the value in CPU ID register field, bits[11:8] of the MPIDR.
CNTHPIRQ[0-3] Signal Master Hypervisor physical timer interrupt.
CNTPNSIRQ[0-3] Signal Master Non-secure physical timer interrupt.
CNTPSIRQ[0-3] Signal Master Secure physical timer interrupt.
cntvalueb CounterInterface Slave Interface to a platform level MemoryMappedCounter module.
CNTVIRQ[0-3] Signal Master Virtual timer interrupt.
commirq[0-3] Signal Master Communications channel receive or transmit interrupt request.
commrx[0-3] Signal Master Communications channel receive.
commtx[0-3] Signal Master Communications channel transmit.
cp15sdisable[0-3] Signal Slave Disables write access to some Secure CP15 registers.
cpuporeset[0-3] Signal Slave Power on reset. Initializes all the processor logic, including debug logic.
cryptodisable[0-3] Signal Slave Cryptography engine disable.a
ctidbgirq[0-3] Signal Master Cross Trigger Interface (CTI) interrupt trigger output.
cti[0-3] v8EmbeddedCrossTrigger_controlprotocol Master Interface to the CTI to a platform level Cross Trigger Matrix (CTM).
dbgack[0-3] Signal Master Debug acknowledge.
dbgen[0-3] Signal Slave Invasive debug enable.
dbgnopwrdwn[0-3] Signal Master Request not to power down the core.
dbgpwrupreq[0-3] Signal Master Request to power-up the core.
dev_debug_s PVBus Slave Debug Advanced Peripheral Bus (APB) as exposed to external debug agents.b
edbgrq[0-3] Signal Slave External debug request.
event Signal Peer Event input and output for wakeup from WFE. This port amalgamates the hardware EVENTI and EVENT0 signals.
fiq[0-3] Signal Slave Processor FIQ signal input.
gicv3_redistributor_s[0-3] GICv3Comms Slave Interface to a platform-level GICv3 component.
irq[0-3] Signal Slave Processor IRQ signal input.
l2flushdone Signal Master Flush of L2 memory system complete.
l2flushreq Signal Slave Request flush of L2 memory system.
l2reset Signal Slave Reset the shared L2 memory system controller.
memorymapped_debug_s PVBus Slave Debug APB as exposed to other system agents.b
niden[0-3] Signal Slave Non-invasive debug enable.
periphbase Value_64 Slave Base address of peripheral memory space, the base address for the GIC CPU Interface registers, which are sampled into the Configuration Base Address Register (CBAR) at reset.
pmuirq[0-3] Signal Master Performance Monitoring Unit interrupt signal.
presetdbg Signal Slave Initialize the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_m0 PVBus Master Bus master that the processor generates transactions on. This port is a PV representation of the AXI master port.
rei[0-3] Signal Slave Individual processor RAM Error Interrupt signal input.
reset[0-3] Signal Slave Individual processor reset.
romaddr Value_64 Slave Debug ROM base address.
romaddrv Signal Slave Debug ROM base address valid.
rvbaraddr[0-3] Value_64 Slave Reset Vector Base Address for executing in AArch64 state. Only sampled at reset.
sei[0-3] Signal Slave Individual processor System Error Interrupt signal input.
smpen[0-3] Signal Master Status of the CPUECTLR.SMPEN bit, whether the processor is SMP enabled.
spiden[0-3] Signal Slave Secure privileged invasive debug enable.
spniden[0-3] Signal Slave Secure privileged non-invasive debug enable.
standbywfe[0-3] Signal Master Indicates that a processor is in Wait For Event state.
standbywfi[0-3] Signal Master Indicates that a processor is in Wait For Interrupt state.
standbywfil2 Signal Master Indicates that all the individual processors and the L2 systems are in a WFI state.
ticks[0-3] InstructionCount Master Instruction count for visualization.
vcpumntirq[0-3] Signal Master Virtual processor interface maintenance interrupt request.
vfiq[0-3] Signal Slave Processor Virtual FIQ signal input.
vinithi[0-3] Signal Slave Initialize with high vectors enabled after reset.
virtio_s PVBus Slave A model-specific port that connects to virtio peripherals in the L2 system. It ensures coherency, with the correct attributes.
virq[0-3] Signal Slave Processor Virtual IRQ signal input.
vsei[0-3] Signal Slave Processor Virtual System Error Interrupt request.

ARMCortexA35xnCT - parameters

This section describes the ARMCortexA35xnCT parameters.

ARMCortexA35xnCT parameters

Table 3-21 ARMCortexA35xnCT parameters

Name Type Allowed values Default value Description
BROADCASTCACHEMAINT bool true, false true Enable broadcasting of cache maintenance operations to downstream caches. The broadcastcachemaint signal overrides this value, if used.
BROADCASTINNER bool true, false true Enable broadcasting of Inner Shareable transactions. The broadcastinner signal overrides this value, if used.
BROADCASTOUTER bool true, false true Enable broadcasting of Outer Shareable transactions. The broadcastouter signal overrides this value, if used.
bus_type uint32_t 0-2 0 Change reset value of L2ACTLR register. 0=ACE, 1=CHI, 2=AXI.
CLUSTER_ID uint32_t 0x0-0xFFFF 0x0 Master ID, bits[23:8] of the MPIDR using bits[15:0] of the CLUSTER_ID value.
cpi_div uint32_t 1-0x7FFFFFFF 1 Divider for calculating Cycles Per Instruction (CPI).
cpi_mul uint32_t 1-0x7FFFFFFF 1 Multiplier for calculating CPI.
DBGROMADDR uint64_t 0x0-0xFFFFFFFFFFFF 0x22000000 Specify bits[43:12] of the top-level ROM table Physical Address.
DBGROMADDRV bool true, false true System samples DBGROMADDR.
dcache-size uint32_t 0x4000-0x100000 0x8000 L1 D-cache size in bytes.
dcache-state_modelled bool true, false false L1 D-cache has stateful implementation.c
GICDISABLE bool true, false true Disable the GIC CPU interface.
icache-size uint32_t 0x4000-0x100000 0x8000 L1 I-cache size in bytes.
icache-state_modelled bool true, false false L1 I-cache has stateful implementation.c
l2cache-size uint32_t 0x0-0x1000000 0x80000 L2 cache size in bytes.
PERIPHBASE uint64_t 0-0xFFFFFFFFFF 0x13080000 Base address of peripheral memory space, the base address for the GIC CPU Interface registers, sampled into the Configuration Base Address Register (CBAR) at reset.

ARMCortexA35xnCT cache latency cluster parameters

Note

  • These latencies are only effective when you enable cache-state modeling.
  • Timing annotation for transactions downstream of the cache models propagates through the cache models.

Table 3-22 ARMCortexA35xnCT cache latency cluster parameters

Parameter Type Allowed values Default value Description
dcache-maintenance_latency uint64_t - 0x0 L1 D-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
dcache-read_latency uint64_t - 0x0 L1 D-cache timing annotation latency for read accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-snoop_data_transfer_latency uint64_t - 0x0 L1 D-cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-write_latency uint64_t - 0x0 L1 D-cache timing annotation latency for write accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
icache-maintenance_latency uint64_t - 0x0 L1 I-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when icache-state_modelled=true.
icache-read_latency uint64_t - 0x0 L1 I-cache timing annotation latency for read accesses given in ticks per byte accessed. For use when icache-state_modelled=true.
l2cache-maintenance_latency uint64_t - 0x0 L2 cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
l2cache-read_latency uint64_t - 0x0 L2 cache timing annotation latency for read accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_data_transfer_latency uint64_t - 0x0 L2 cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_issue_latency uint64_t - 0x0 L2 cache timing annotation latency for snoop accesses issued by this cache in total ticks. For use when dcache-state_modelled=true.
l2cache-write_latency uint64_t - 0x0 L2 cache timing annotation latency for write accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.

ARMCortexA35xnCT core parameters

Table 3-23 ARMCortexA35xnCT core parameters

Named Type Allowed values Default value Description
AA64nAA32 bool true, false true Register width state after reset.
CFGEND bool true, false false Endianness configuration at reset. It sets the initial value of the EE bits in the CP15 SCTLR_EL3 and SCTR_S registers after a reset.
CFGTE bool true, false false Initialize to take exceptions in T32 state after reset.
CP15SDISABLE bool true, false false Disable write access to some Secure CP15 registers.
CRYPTODISABLE bool true, false false Disable ARMv8 Cryptography Extensions.e
max_code_cache uint32_t 0x0-0xFFFFFFFFFFFFFFFF 0x16777216 Maximum number of bytes used for caching code translations.
min_sync_level uint32_t 0-3 0 The minimum syncLevel.
RVBARADDR uint64_t 0x0-0xFFFFFFFFFFFFFFFF 0x0 Reset Vector Base Address for executing in AArch64 state.
semihosting-ARM_SVC uint32_t 0x0-0xFFFFFF 0x123456 A32 SVC number for semihosting.
semihosting-cmd_line string No limit except memory "" Command line available to semihosting.
semihosting-cwd string No limit except memory "" Default working directory for semihosting.f g
semihosting-enable bool true, false true Enable semihosting traps.
semihosting-heap_base uint32_t 0x0-0xFFFFFFFF 0x0 Virtual address of semihosting heap base.
semihosting-heap_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 Virtual address of semihosting top of heap.
semihosting-stack_base uint32_t 0x0-0xFFFFFFFF 0x10000000 Virtual address of semihosting base of descending stack.
semihosting-stack_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 Virtual address of semihosting stack limit.
semihosting-Thumb_SVC uint32_t 0x0-0xFF 0xAB T32 SVC number for semihosting.
vfp-enable_at_reset bool true, false false All implementation operations required in order to enable FP and ASE support are performed implicitly by the model.h
VINITHI bool true, false false Initialize with high vectors enabled after reset.

ARMCortexA35xnCT TLB latency cluster parameters

Note

Timing annotation for transactions downstream of the TLB model propagates through the TLB model.

Table 3-24 ARMCortexA35xnCT TLB latency cluster parameters

Parameter Type Allowed values Default value Description
ptw_latency uint32_t - 0x0 Page table walker latency for Timing Annotation (TA), in simulation ticks.
tlb_latency uint32_t - 0x0 TLB latency for TA, in simulation ticks.
a ARMv8 Cryptography Extensions require a separate package, which is subject to export license conditions. Contact ARM for details.
b The system designer decides whether a debug APB ties the external debug view with other system views. In the model, use a PVBusDecoder to direct traffic to the correct port.
c  If either L1 cache is stateful, then the L2 cache is stateful.
d Precede these names with cpun., where n is between 0 and 3.
e ARMv8 Cryptography Extensions require a separate package, which is subject to export license conditions. Contact ARM for details.
f The host operating system limits the maximum path length.
g The semihosting-cwd option does not provide any security. Software running on the model can access files outside this directory using relative paths containing “..” or using absolute paths.
h This is a model-specific option that has no hardware equivalent. ARM recommends that it is only used in test systems and tied off to false in production systems.
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