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ARMCortexA53xnCT component

This section describes the ARMCortexA53xnCT component.

ARMCortexA53xnCT - about

This C++ component is a model of r0p1 of an ARMv8-A Cortex®-A53 processor containing from one to four cores. The n shows the number of cores.

ARMCortexA53xnCT - ports

This section describes the ports.

Table 3-17 ARMCortexA53xnCT ports

Name Protocol Type Description
aa64naa32[0-3] Signal Slave Register width state after reset.
acp_s PVBus Slave Bus slave that the processor receives coherency transactions on. It is a Programmer’s View (PV) of the Advanced Extensible Interface (AXI) Accelerator Coherency Port (ACP) slave port.
broadcastinner Signal Slave Enable broadcasting of inner shareable transactions.
broadcastouter Signal Slave Enable broadcasting of outer shareable transactions.
broadcastcachemaint Signal Slave Enable broadcasting of cache maintenance operations to downstream caches.
cfgend[0-3] Signal Slave Configure endianness at reset: set the value of the EE bits in the CP15 SCTLR_EL3 and SCTR_S registers.
cfgsdisable Signal Slave This signal disables write access to some secure Interrupt Controller registers.
cfgte[0-3] Signal Slave Initialize to take exceptions in T32 state after reset.
clk_in ClockSignal Slave Processor clock input, for determining the rate of instruction execution relative to other system components.
clrexmonack Signal Master Acknowledge handshake signal for the clrexmonreq signal.
clrexmonreq Signal Slave Signals the clearing of an external global exclusive monitor.
clusterid Value Slave Master ID, bits[23:8] of the MPIDR using bits[15:0] of the CLUSTERID value.
CNTHPIRQ[0-3] Signal Master Hypervisor physical timer interrupt.
CNTPNSIRQ[0-3] Signal Master Secure physical timer interrupt.
CNTPSIRQ[0-3] Signal Master Non-secure physical timer interrupt.
cntvalueb CounterInterface Slave Interface to a platform level MemoryMappedCounter module.
CNTVIRQ[0-3] Signal Master Virtual timer interrupt.
commirq[0-3] Signal Master Communications channel receive or transmit interrupt request.
commrx[0-3] Signal Master Communications channel receive.
commtx[0-3] Signal Master Communications channel transmit.
cp15sdisable[0-3] Signal Slave Disables write access to some Secure CP15 registers.
cpuporeset[0-3] Signal Slave Power on reset. Initializes all the processor logic, including debug logic.
cryptodisable[0-3] Signal Slave Cryptography engine disable.a
ctidbgirq[0-3] Signal Master Cross Trigger Interface (CTI) interrupt trigger output.
cti[0-3] v8EmbeddedCrossTrigger_controlprotocol Master Interface to the CTI to a platform level Cross Trigger Matrix (CTM).
dbgack[0-3] Signal Master Debug acknowledge.
dbgen[0-3] Signal Slave Invasive debug enable.
dbgnopwrdwn[0-3] Signal Master This signal relates to core power down.
dbgpwrupreq[0-3] Signal Master This signal relates to core power up.
dbgromaddr Value_64 Slave Specify bits[43:12] of the top-level ROM table physical address.
dbgromaddrv Signal Slave Valid signal for dbgromaddr.
dev_debug_s PVBus Slave Debug Advanced Peripheral Bus (APB) as exposed to external debug agents.b
edbgrq[0-3] Signal Slave External debug request.
event Signal Peer Event input and output for wakeup from WFE. This port amalgamates the hardware EVENTI and EVENT0 signals.
fiq[0-3] Signal Slave Processor FIQ signal input.
gicv3_redistributor_s[0-3] GICv3Comms Slave Interface to a platform-level GICv3 component.
irq[0-3] Signal Slave Processor IRQ signal input.
l2flushreq Signal Slave Request flush of L2 memory system.
l2flushdone Signal Master Flush of L2 memory system complete.
l2reset Signal Slave Reset the shared L2 memory system controller.
memorymapped_debug_s PVBus Slave Debug APB as exposed to other system agents.b
niden[0-3] Signal Slave Non-invasive debug enable.
periphbase Value_64 Slave Base address of peripheral memory space, the base address for the GIC CPU Interface registers, which are sampled into the Configuration Base Address Register (CBAR) at reset.
pmuirq[0-3] Signal Master Performance Monitoring Unit interrupt signal.
presetdbg Signal Slave Initialize the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_m0 PVBus Master Bus master that the processor generates transactions on. This port is a PV representation of the AXI master port.
rei[0-3] Signal Slave Individual processor RAM Error Interrupt signal input.
reset[0-3] Signal Slave Individual processor reset.
romaddr Value_64 Slave Debug ROM base address.
romaddrv Signal Slave Debug ROM base address valid.
rvbaraddr[0-3] Value_64 Slave Reset Vector Base Address for executing in AArch64 state. Only sampled at reset.
sei[0-3] Signal Slave Individual processor System Error Interrupt signal input.
smpen[0-3] Signal Master Status of the CPUECTLR.SMPEN bit, whether the processor is SMP enabled.
spiden[0-3] Signal Slave Secure privileged invasive debug enable.
spniden[0-3] Signal Slave Secure privileged non-invasive debug enable.
standbywfe[0-3] Signal Master Indicates if a processor is in Wait For Event state.
standbywfi[0-3] Signal Master Indicates if a processor is in Wait For Interrupt state.
standbywfil2 Signal Master Indicate that all the individual processors and the L2 systems are in a WFI state.
ticks[0-3] InstructionCount Master Instruction count for visualization.
vcpumntirq[0-3] Signal Master Virtual processor interface maintenance interrupt request.
vinithi[0-3] Signal Slave Initialize with high vectors enabled after reset.
virtio_s PVBus Slave A model-specific port that connects to virtio peripherals in the L2 system. It ensures coherency, with the correct attributes.
vfiq[0-3] Signal Slave Processor Virtual FIQ signal input.
virq[0-3] Signal Slave Processor Virtual IRQ signal input.
vsei[0-3] Signal Slave Processor Virtual System Error Interrupt request.

ARMCortexA53xnCT - parameters

This section describes the parameters.

Table 3-18 ARMCortexA53xnCT cluster parameters

Name Type Default value Description
BROADCASTCACHEMAINT bool 0x1 Enable broadcasting of cache maintenance operations to downstream caches. The broadcastcachemaint signal will override this value if used.
BROADCASTINNER bool 0x1 Enable broadcasting of Inner Shareable transactions. The broadcastinner signal will override this value if used.
BROADCASTOUTER bool 0x1 Enable broadcasting of Outer Shareable transactions. The broadcastouter signal will override this value if used.
CLUSTER_ID int 0x0 Processor cluster ID value
DBGROMADDR int 0x0 Initialization value of DBGDRAR register. Bits[47:12] of this register specify the ROM table physical address.
DBGROMADDRV bool 0x0 If true, set bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid
GICDISABLE bool 0x1 Disable the new style GICv3 CPU interface in each core model. Should be left enabled unless the platform contains a GICv3 distributor.
PERIPHBASE int 0x13080000 Base address of peripheral memory space
bus_type int 0x0 Cosmetic change that changes reset value of L2ACTLR register. 0, ACE. 1, CHI. 2, AXI
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dcache-hit_latency int 0x0 L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when dcache-state_modelled=true.
dcache-maintenance_latency int 0x0 L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
dcache-miss_latency int 0x0 L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when dcache-state_modelled=true.
dcache-prefetch_enabled bool 0x0 Enable simulation of data cache prefetching. This is only used when dcache-state_modelled=true
dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access (of size dcache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when dcache-state_modelled=true.
dcache-read_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when dcache-state_modelled=true.
dcache-size int 0x8000 L1 D-Cache size in bytes.
dcache-snoop_data_transfer_latency int 0x0 L1 D-Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access (of size dcache-write_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-write_latency is set. This is only used when dcache-state_modelled=true.
dcache-write_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when dcache-state_modelled=true.
icache-hit_latency int 0x0 L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when icache-state_modelled=true.
icache-maintenance_latency int 0x0 L1 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when icache-state_modelled=true.
icache-miss_latency int 0x0 L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when icache-state_modelled=true.
icache-prefetch_enabled bool 0x0 Enable simulation of instruction cache prefetching. This is only used when icache-state_modelled=true.
icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access (of size icache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when icache-state_modelled=true.
icache-read_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when icache-state_modelled=true.
icache-size int 0x8000 L1 I-Cache size in bytes.
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
l2cache-hit_latency int 0x0 L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2cache-state_modelled=true.
l2cache-maintenance_latency int 0x0 L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
l2cache-miss_latency int 0x0 L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2cache-state_modelled=true.
l2cache-read_access_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when l2cache-state_modelled=true.
l2cache-read_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2cache-state_modelled=true.
l2cache-size int 0x80000 L2 Cache size in bytes.
l2cache-snoop_data_transfer_latency int 0x0 L2 Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
l2cache-snoop_issue_latency int 0x0 L2 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when dcache-state_modelled=true.
l2cache-write_access_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-write_latency is set. This is only used when l2cache-state_modelled=true.
l2cache-write_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2cache-state_modelled=true.
patch_level int 0x1 Cosmetic change to patch number in MIDR/MIDR_EL1. Corresponds to the Y in rXpY.
ptw_latency int 0x0 Page table walker latency for TA (Timing Annotation), expressed in simulation ticks
revision_number int 0x0 Cosmetic change to revision number in MIDR/MIDR_EL1. Corresponds to the X in rXpY.
tlb_latency int 0x0 TLB latency for TA (Timing Annotation), expressed in simulation ticks
walk_cache_latency int 0x0 Walk cache latency for TA (Timing Annotation), expressed in simulation ticks

Table 3-19 ARMCortexA53xnCT core parameters

In the following table, the core identifier, n can be in the range 0-3.
Name Type Default value Description
cpun.AA64nAA32 bool 0x1 Register width configuration at reset. 0, AArch32. 1, AArch64.
cpun.CFGEND bool 0x0 Endianness configuration at reset. 0, little endian. 1, big endian.
cpun.CFGTE bool 0x0 Instruction set state when resetting into AArch32. 0, A32. 1, T32.
cpun.CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
cpun.CRYPTODISABLE bool 0x0 Disable cryptographic features.
cpun.RVBARADDR int 0x0 Value of RVBAR_ELx register.
cpun.VINITHI bool 0x0 Reset value of SCTLR.V.
cpun.max_code_cache int 0x4000000 Maximum number of bytes for caching code translations.
cpun.min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpun.semihosting-A32_HLT int 0xf000 A32 HLT number for semihosting calls.
cpun.semihosting-A64_HLT int 0xf000 A64 HLT number for semihosting calls.
cpun.semihosting-ARM_SVC int 0x123456 A32 SVC number for semihosting calls.
cpun.semihosting-T32_HLT int 0x3c T32 HLT number for semihosting calls.
cpun.semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting calls.
cpun.semihosting-cmd_line string "" Command line available to semihosting calls.
cpun.semihosting-cwd string "" Base directory for semihosting file access.
cpun.semihosting-enable bool 0x1 Enable semihosting SVC/HLT traps.
cpun.semihosting-heap_base int 0x0 Virtual address of heap base.
cpun.semihosting-heap_limit int 0xf000000 Virtual address of top of heap.
cpun.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack.
cpun.semihosting-stack_limit int 0xf000000 Virtual address of stack limit.
cpun.vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: ARM recommends going though the implementation's suggested VFP power-up sequence!

ARMCortexA53xnCT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the ETM registers and the integration and test registers.

ARMCortexA53xnCT - caches

This component implements representative L1 and L2 caches.

ARMCortexA53xnCT - debug features

This component exports a CADI debug interface.

ARMCortexA53xnCT - debug - registers

All modeled registers are visible in the debugger.

ARMCortexA53xnCT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexA53xnCT - debug - memory

This component presents virtual and physical views of memory.

The virtual views are:

  • Secure Monitor.
  • NS Hyp.
  • Guest.

These views are 264 bytes in size.

The physical views are:

  • Physical Memory (Secure).
  • Physical Memory (Non-secure).

These views are 264 bytes in size, however the maximum physical address permissible by the Cortex-A53 processor is 240 — 1.

ARMCortexA53xnCT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of Linux on an example system.

ARMCortexA53xnCT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • The value of the AArch64 PMCEID0_EL0 register, and the AArch32 alias of this register, differs in the model from the TRM value. The model value reflects the model counters.
  • The mechanisms for setting the affinity fields of the MPIDR. The RTL has two ports:
    • CLUSTERIDAFF1[7:0].

    • CLUSTERIDAFF2[7:0].
    AFF1 sets the value of MPIDR bits[15:8] and AFF2 sets the value of MPIDR bits[23:16]. In contrast, the model has a single CLUSTER_ID port. This difference allows the setting of bits[23:8] of the MPIDR using bits[15:0] of the CLUSTER_ID value.
  • The memory mapped debug registers have a view for cores and a view for external debug agents. In the model, these views require two PVBus ports. In hardware, the system designer decides how the implementation differentiates the views.
  • In the model, a single peer event port combines the functionality of the eventi and evento signals in the RTL.
  • The Generic Timers are Programmer’s View (PV) level abstractions: a model-specific protocol connects the cntvalueb port to the MemoryMappedCounterModule.
  • The GIC CPU Interface is a PV level abstraction: a model-specific protocol connects the GIC CPU Interface to the GIC Distributor.
  • The CoreSight Cross Trigger Interface (CTI) is a PV level abstraction: the interface is a model specific one.
  • The model has no mechanism to read the internal memory that the Cache and TLB structures use, through the implementation defined region of the system coprocessor interface. This memory includes the RAM Index Register, IL1DATA Registers, DL1DATA Registers, and associated functionality.
  • The model does not implement:
    • ETM registers.
    • The PMUEVENT bus.
    • The WARMRESETREQ signal. However, the warm reset code sequence (see the section Code sequence to request a Warm reset as a result of RMR_ELx.RR in the ARMv8-A Architecture Reference Manual) makes the model simulate a warm reset of the core.
    • The PMUSNAPSHOTREQ and PMUSNAPSHOTACK signals.
    • The EXTERRIRQ and INTERRIRQ signals.
    • Processor dynamic-retention signals.
    • The SYSBARDISABLE signal.
    • The DBGPWRDUP, DBGPWRUPREQ, DBGNOPWRDWN, and DBGRSTREQ debug power management signals.
    • The RTL synthesis option to remove FP and ASE.
    • The RTL synthesis option for a Cortex-A15 style debug memory map.
a ARMv8 Cryptography Extensions require a separate package, which is subject to export license conditions. Contact ARM for details.
b The system designer decides whether a debug APB ties the external debug view with other system views. In the model, use a PVBusDecoder to direct traffic to the correct port.
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