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ARMCortexA57xnCT component

This section describes the ARMCortexA57xnCT component.

ARMCortexA57xnCT - about

This component is a model of r0p0 of an ARMv8-A Cortex®-A57 processor containing from one to four cores. The n shows the number of cores.

ARMCortexA57xnCT - ports

This section describes the ports.

Table 3-14 ARMCortexA57xnCT ports

Name Protocol Type Description
aa64naa32[0-3] Signal Slave Register width state after reset.
acp_s PVBus Slave Bus slave that the processor receives coherency transactions on. It is a Programmer’s View (PV) of the Advanced Extensible Interface (AXI) Accelerator Coherency Port (ACP) slave port.
broadcastinner Signal Slave Enable broadcasting of inner shareable transactions.
broadcastouter Signal Slave Enable broadcasting of outer shareable transactions.
broadcastcachemaint Signal Slave Enable broadcasting of cache maintenance operations to downstream caches.
cfgend[0-3] Signal Slave Configure endianness at reset: set the value of the EE bits in the CP15 SCTLR_EL3 and SCTR_S registers.
cfgsdisable Signal Slave This signal disables write access to some secure Interrupt Controller registers.
cfgte[0-3] Signal Slave Initialize to take exceptions in T32 state after reset.
clk_in ClockSignal Slave Processor clock input, for determining the rate of instruction execution relative to other system components.
clrexmonack Signal Master Acknowledge handshake signal for the clrexmonreq signal.
clrexmonreq Signal Slave Signals the clearing of an external global exclusive monitor.
clusterid Value Slave Master ID, bits[23:8] of the MPIDR using bits[15:0] of the CLUSTERID value.
CNTHPIRQ[0-3] Signal Master Hypervisor physical timer interrupt.
CNTPNSIRQ[0-3] Signal Master Secure physical timer interrupt.
CNTPSIRQ[0-3] Signal Master Non-secure physical timer interrupt.
cntvalueb CounterInterface Slave Interface to a platform level MemoryMappedCounter module.
CNTVIRQ[0-3] Signal Master Virtual timer interrupt.
commirq[0-3] Signal Master Communications channel receive or transmit interrupt request.
commrx[0-3] Signal Master Communications channel receive.
commtx[0-3] Signal Master Communications channel transmit.
cp15sdisable[0-3] Signal Slave Disables write access to some Secure CP15 registers.
cpuporeset[0-3] Signal Slave Power on reset. Initializes all the processor logic, including debug logic.
cryptodisable[0-3] Signal Slave Cryptography engine disable.a
ctidbgirq[0-3] Signal Master Cross Trigger Interface (CTI) interrupt trigger output.
cti[0-3] v8EmbeddedCrossTrigger_controlprotocol Master Interface to the CTI to a platform level Cross Trigger Matrix (CTM).
dbgack[0-3] Signal Master Debug acknowledge.
dbgen[0-3] Signal Slave Invasive debug enable.
dbgnopwrdwn[0-3] Signal Master This signal relates to core power down.
dbgpwrupreq[0-3] Signal Master This signal relates to core power up.
dbgromaddr Value_64 Slave Specify bits[43:12] of the top-level ROM table physical address.
dbgromaddrv Signal Slave Valid signal for dbgromaddr.
dev_debug_s PVBus Slave Debug Advanced Peripheral Bus (APB) as exposed to external debug agents.b
edbgrq[0-3] Signal Slave External debug request.
event Signal Peer Event input and output for wakeup from WFE. This port amalgamates the hardware EVENTI and EVENT0 signals.
fiq[0-3] Signal Slave Processor FIQ signal input.
gicv3_redistributor_s[0-3] GICv3Comms Slave Interface to a platform-level GICv3 component.
irq[0-3] Signal Slave Processor IRQ signal input.
l2flushreq Signal Slave Request flush of L2 memory system.
l2flushdone Signal Master Flush of L2 memory system complete.
l2reset Signal Slave Reset the shared L2 memory system controller.
memorymapped_debug_s PVBus Slave Debug APB as exposed to other system agents.b
niden[0-3] Signal Slave Non-invasive debug enable.
periphbase Value_64 Slave Base address of peripheral memory space, the base address for the GIC CPU Interface registers, which are sampled into the Configuration Base Address Register (CBAR) at reset.
pmuirq[0-3] Signal Master Performance Monitoring Unit interrupt signal.
presetdbg Signal Slave Initialize the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_m0 PVBus Master Bus master that the processor generates transactions on. This port is a PV representation of the AXI master port.
rei[0-3] Signal Slave Individual processor RAM Error Interrupt signal input.
reset[0-3] Signal Slave Individual processor reset.
romaddr Value_64 Slave Debug ROM base address.
romaddrv Signal Slave Debug ROM base address valid.
rvbaraddr[0-3] Value_64 Slave Reset Vector Base Address for executing in AArch64 state. Only sampled at reset.
sei[0-3] Signal Slave Individual processor System Error Interrupt signal input.
smpen[0-3] Signal Master Status of the CPUECTLR.SMPEN bit, whether the processor is SMP enabled.
spiden[0-3] Signal Slave Secure privileged invasive debug enable.
spniden[0-3] Signal Slave Secure privileged non-invasive debug enable.
standbywfe[0-3] Signal Master Indicates if a processor is in Wait For Event state.
standbywfi[0-3] Signal Master Indicates if a processor is in Wait For Interrupt state.
standbywfil2 Signal Master Indicate that all the individual processors and the L2 systems are in a WFI state.
ticks[0-3] InstructionCount Master Instruction count for visualization.
vcpumntirq[0-3] Signal Master Virtual processor interface maintenance interrupt request.
vinithi[0-3] Signal Slave Initialize with high vectors enabled after reset.
virtio_s PVBus Slave A model-specific port that connects to virtio peripherals in the L2 system. It ensures coherency, with the correct attributes.
vfiq[0-3] Signal Slave Processor Virtual FIQ signal input.
virq[0-3] Signal Slave Processor Virtual IRQ signal input.
vsei[0-3] Signal Slave Processor Virtual System Error Interrupt request.

ARMCortexA57xnCT - parameters

This section describes the parameters.

Table 3-15 ARMCortexA57xnCT cluster parameters

Note

  • The cache latency parameters are only effective when you enable cache-state modeling.
  • Timing annotation for transactions downstream of the cache and TLB models propagates through the cache models.
Name Type Default value Description
BROADCASTCACHEMAINT bool 0x1 Enable broadcasting of cache maintenance operations to downstream caches. The broadcastcachemaint signal will override this value if used.
BROADCASTINNER bool 0x1 Enable broadcasting of Inner Shareable transactions. The broadcastinner signal will override this value if used.
BROADCASTOUTER bool 0x1 Enable broadcasting of Outer Shareable transactions. The broadcastouter signal will override this value if used.
CLUSTER_ID int 0x0 Processor cluster ID value
DBGROMADDR int 0x0 Initialization value of DBGDRAR register. Bits[47:12] of this register specify the ROM table physical address.
DBGROMADDRV bool 0x0 If true, set bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid
GICDISABLE bool 0x1 Disable the new style GICv3 CPU interface in each core model. Should be left enabled unless the platform contains a GICv3 distributor.
PERIPHBASE int 0x13080000 Base address of peripheral memory space
bus_type int 0x0 Cosmetic change that changes reset value of L2ACTLR register. 0, ACE. 1, CHI. 2, AXI
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dcache-hit_latency int 0x0 L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when dcache-state_modelled=true.
dcache-maintenance_latency int 0x0 L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
dcache-miss_latency int 0x0 L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when dcache-state_modelled=true.
dcache-prefetch_enabled bool 0x0 Enable simulation of data cache prefetching. This is only used when dcache-state_modelled=true
dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access (of size dcache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when dcache-state_modelled=true.
dcache-read_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when dcache-state_modelled=true.
dcache-snoop_data_transfer_latency int 0x0 L1 D-Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access (of size dcache-write_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-write_latency is set. This is only used when dcache-state_modelled=true.
dcache-write_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when dcache-state_modelled=true.
icache-hit_latency int 0x0 L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when icache-state_modelled=true.
icache-maintenance_latency int 0x0 L1 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when icache-state_modelled=true.
icache-miss_latency int 0x0 L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when icache-state_modelled=true.
icache-prefetch_enabled bool 0x0 Enable simulation of instruction cache prefetching. This is only used when icache-state_modelled=true.
icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access (of size icache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when icache-state_modelled=true.
icache-read_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when icache-state_modelled=true.
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
l2cache-hit_latency int 0x0 L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2cache-state_modelled=true.
l2cache-maintenance_latency int 0x0 L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
l2cache-miss_latency int 0x0 L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2cache-state_modelled=true.
l2cache-read_access_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, This is only used when l2cache-state_modelled=true.
l2cache-read_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2cache-state_modelled=true.
l2cache-size int 0x80000 L2 Cache size in bytes.
l2cache-snoop_data_transfer_latency int 0x0 L2 Cache timing annotation latency for received snoop accesses that perfom a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
l2cache-snoop_issue_latency int 0x0 L2 Cache timing annotation latency for snoop accesses issued by this cache in total ticks. This is only used when dcache-state_modelled=true.
l2cache-write_access_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2cache-write_latency is set. This is only used when l2cache-state_modelled=true.
l2cache-write_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2cache-state_modelled=true.
ptw_latency int 0x0 Page table walker latency for TA (Timing Annotation), expressed in simulation ticks
tlb_latency int 0x0 TLB latency for TA (Timing Annotation), expressed in simulation ticks
walk_cache_latency int 0x0 Walk cache latency for TA (Timing Annotation), expressed in simulation ticks

Table 3-16 ARMCortexA57xnCT core parameters

In the following table, the core identifier, n can be in the range 0-3.
Name Type Default value Description
cpun.AA64nAA32 bool 0x1 Register width configuration at reset. 0, AArch32. 1, AArch64.
cpun.CFGEND bool 0x0 Endianness configuration at reset. 0, little endian. 1, big endian.
cpun.CFGTE bool 0x0 Instruction set state when resetting into AArch32. 0, A32. 1, T32.
cpun.CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
cpun.CRYPTODISABLE bool 0x0 Disable cryptographic features.
cpun.RVBARADDR int 0x0 Value of RVBAR_ELx register.
cpun.VINITHI bool 0x0 Reset value of SCTLR.V.
cpun.max_code_cache int 0x4000000 Maximum number of bytes for caching code translations.
cpun.min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpun.semihosting-A32_HLT int 0xf000 A32 HLT number for semihosting calls.
cpun.semihosting-A64_HLT int 0xf000 A64 HLT number for semihosting calls.
cpun.semihosting-ARM_SVC int 0x123456 A32 SVC number for semihosting calls.
cpun.semihosting-T32_HLT int 0x3c T32 HLT number for semihosting calls.
cpun.semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting calls.
cpun.semihosting-cmd_line string "" Command line available to semihosting calls.
cpun.semihosting-cwd string "" Base directory for semihosting file access.
cpun.semihosting-enable bool 0x1 Enable semihosting SVC/HLT traps.
cpun.semihosting-heap_base int 0x0 Virtual address of heap base.
cpun.semihosting-heap_limit int 0xf000000 Virtual address of top of heap.
cpun.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack.
cpun.semihosting-stack_limit int 0xf000000 Virtual address of stack limit.
cpun.vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: ARM recommends going though the implementation's suggested VFP power-up sequence!

ARMCortexA57xnCT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the ETM registers and the integration and test registers.

ARMCortexA57xnCT - caches

This component implements representative L1 and L2 caches.

ARMCortexA57xnCT - debug features

This component exports a CADI debug interface.

ARMCortexA57xnCT - debug - registers

All modeled registers are visible in the debugger.

ARMCortexA57xnCT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexA57xnCT - debug - memory

This component presents virtual and physical views of memory.

The virtual views are:

  • Secure Monitor.
  • NS Hyp.
  • Guest.

These views are 264 bytes in size.

The physical views are:

  • Physical Memory (Secure).
  • Physical Memory (Non-secure).

These views are 264 bytes in size, however the maximum physical address permissible by the Cortex-A57 processor is 244 — 1.

ARMCortexA57xnCT - trace sources

This section describes the trace sources for the ARM_Cortex-A57.

ASYNC_MEMORY_FAULT

Context ID Register write. Fields:

FAULT unsigned int
Fault status in ESR format.
VADDR signed int
Virtual Address (or 0 if unavailable).
PADDR unsigned int
Physical Address (or 0 if unavailable).

ArchMsg.Warning.Unpredictably Indexed PM Event Register

Fields:

SEL unsigned int
Selector.
IsDirect unsigned int
Direct Access rather than indirect.
N unsigned int
Number of Accessible Registers.

ArchMsg.Warning.branch_to_unaligned_address

Fields:

ADDR unsigned int
Unaligned branch address.

ArchMsg.Warning.cache_contents_unknown

Fields:

SIDE unsigned int
0 d-side cache or unified cache, 1 i-side.
REGIME unsigned int
Current translation regime.

ArchMsg.Warning.dcimvac_matches_watchpoint

Watchpoints matching an AArch32 DCIMVA are implementation defined.

ArchMsg.Warning.decode_fracbitsnegative

VCVT Instruction is unpredictable with a negative number of fraction bits.

ArchMsg.Warning.decode_initblock

Instruction is unpredictable in an IT block.

ArchMsg.Warning.decode_initblocknotlast

Instruction is unpredictable in an IT block when not the last.

ArchMsg.Warning.decode_invalid_condition

Instruction is unpredictable when the condition is not AL.

ArchMsg.Warning.decode_invalidfieldcombination

Instruction is unpredictable with the values in %{FIELD1} and %{FIELD2}. Fields:

FIELD1 enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ
FIELD2 enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ

ArchMsg.Warning.decode_invalidvalue

Instruction is unpredictable with the value in %{FIELD}. Fields:

FIELD enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ

ArchMsg.Warning.decode_mem_hint_unallocated

There is no memory hint allocated to this bit pattern.

ArchMsg.Warning.decode_registermatch

Instruction is unpredictable with %{FIELD1} and %{FIELD2} as the same register. Fields:

FIELD1 enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ
FIELD2 enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ

ArchMsg.Warning.decode_registermismatch

Instruction is unpredictable with %{FIELD1} and %{FIELD2} as different registers. Fields:

FIELD1 enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ
FIELD2 enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ

ArchMsg.Warning.decode_registeroutofrange

Float point instruction is unpredictable indexing beyond the end of the register bank.

ArchMsg.Warning.decode_sbzsbo

Reserved bits in the instruction are not canonical.

ArchMsg.Warning.decode_transactiontoobig

Attempt to perform a memory transaction of more than 128 bytes.

ArchMsg.Warning.decode_unpred_other

Instruction is unpredictable.

ArchMsg.Warning.decode_unpreduseofpc

Instruction is unpredictable when %{FIELD} is PC. Fields:

FIELD enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ

ArchMsg.Warning.decode_unpreduseofr13

Instruction is unpredictable when %{FIELD} is R13. Fields:

FIELD enum
Field name.
0x0
UNUSED_FIELDID
0x1
RN
0x2
RM
0x3
RA
0x4
RS
0x5
RD
0x6
RDLO
0x7
RDHI
0x8
RT
0x9
RT2
0xa
MSB
0xb
LSB
0xc
WIDTHM1
0xd
IMM12
0xe
W
0xf
P
0x10
MASK
0x11
SZ

ArchMsg.Warning.decode_unpreduseofr13inreglist

Instruction is unpredictable with R13 in register-list.

ArchMsg.Warning.decode_writebackandbaseinlist

Instruction is unpredictable with write back when the base register is in the transfer list.

ArchMsg.Warning.decode_zeroregistersinlist

Instruction is unpredictable when no registers are to be transferred.

ArchMsg.Warning.recursive_branch

An instruction is performing a branch that targets the same instruction. If this was intended then a WFI might be more effective. Fields:

PC unsigned int
Address of instruction causing the branch.

ArchMsg.Warning.recursive_exception

An instruction has generated an exception that targets the same instruction. Fields:

PC unsigned int
Address of instruction causing the exception.
CPSR unsigned int
Processor state.
TYPE enum
Type of exception.
0x4
undefined instruction
0xc
prefetch abort

ArchMsg.Warning.reentrant_vector_catch

Vector catch debug event on Prefetch or Data abort vector %{ADDR}. Fields:

ADDR unsigned int
vector address.

ArchMsg.Warning.reserved_it_state

Execution with reserved IT state %{ITSTATE}. Fields:

ITSTATE unsigned int
reserved IT state.

ArchMsg.Warning.tlb_contents_unknown

Fields:

VMID unsigned int
Current VMID if applicable.
REGIME unsigned int
Current translation regime.
INVALIDITY unsigned int
Which TLB may be invalid (if TLBs are separate).

ArchMsg.Warning.unknown_DLR_DSPSR

Exiting debug state with unknown DLR or DSPSR.

ArchMsg.Warning.unknown_ELR_SPSR

Returning from debug exception with unknown ELR or SPSR.

ArchMsg.Warning.unpredictable_banked_register_access

Fields:

R unsigned int
R bit.
SYSM unsigned int
SYSm.

ArchMsg.Warning.unpredictable_ccfail_undef

An instruction %{OPCODE} at VA=%{VADDR} failed its condition codes check but would otherwise have caused a non-data-dependent trap or undefined exception. Behavior is implementation-defined choice of exception or nop. Fields:

VADDR unsigned int
Virtual address of the instruction being executed.
OPCODE unsigned int
opcode of the instruction.

ArchMsg.Warning.unpredictable_t32_breakpoint_bas

Unpredictable breakpoint byte address select on a T32 instruction at %{ADDR} with DBGBCR%{N:d}=%{DBGBCR}, DBGBVR%{N:d}=%{DBGBVR}. Fields:

ADDR unsigned int
Address.
N unsigned int
Breakpoint number.
DBGBCR unsigned int
Breakpoint control register.
DBGBVR unsigned int
Breakpoint value register.
ADDR unsigned int
Address.
N unsigned int
Breakpoint number.
DBGBCR unsigned int
Breakpoint control register.
DBGBVR unsigned int
Breakpoint value register.

ArchMsg.Warning.unpredictable_t32_breakpoint_bas

Unpredictable breakpoint byte address select on a T32 instruction at %{ADDR} with DBGBCR%{N:d}=%{DBGBCR}, DBGBVR%{N:d}=%{DBGBVR}. Fields:

ADDR unsigned int
Address.
N unsigned int
Breakpoint number.
DBGBCR unsigned int
Breakpoint control register.
DBGBVR unsigned int
Breakpoint value register.
ADDR unsigned int
Address.
N unsigned int
Breakpoint number.
DBGBCR unsigned int
Breakpoint control register.
DBGBVR unsigned int
Breakpoint value register.

ArchMsg.Warning.unpredictable_watchpoint_far

The value for FAR/EDWAR for hitting this watchpoint may be anywhere in the range %{LOWER_BOUND} to %{UPPER_BOUND}. Fields:

LOWER_BOUND unsigned int
the lowest address accessed by the instruction that triggered the watchpoint.
UPPER_BOUND unsigned int
the highest watchpointed address accessed by that instruction.

ArchMsg.Warning.warning_AdvSIMDExpandImmUnexpectedZero

AdvSIMDExpandImm may treat this immediate value as UNPREDICTABLE.

ArchMsg.Warning.warning_ConditionalSMC

SMC instruction has UNPREDICTABLE effects when conditional when combined with traps.

ArchMsg.Warning.warning_access_crosses_page_boundary

Access crosses page boundary.

ArchMsg.Warning.warning_access_crosses_page_boundary_has_fault

Access crosses page boundary has fault(s).

ArchMsg.Warning.warning_access_crosses_page_boundary_spanning_different_memory

Access at address %{ADDR} crosses page from MEM_TYPE %{MEMTYPE_PAGE1} to %{MEMTYPE_PAGE2}. Fields:

ADDR unsigned int
address of access crossing page.
MEMTYPE_PAGE1 signed int
First Page's memory type (0-Normal, 1-Non-Normal).
MEMTYPE_PAGE2 signed int
Second Page's memory type (0-Normal, 1-Non-Normal).

ArchMsg.Warning.warning_access_wraps_around_memory

Access wraps around memory in %{WIDTH:d}bit mode. Fields:

WIDTH unsigned int
Address width.

ArchMsg.Warning.warning_bx_from_thumbee

BX from ThumbEE to ARM at %{ADDR}. Fields:

ADDR unsigned int
Destination address.

ArchMsg.Warning.warning_ccsidr_unimplemented_level

CCSIDR read while CSSELR %{CSSELR:x} points to an unimplemented cache level. Fields:

CSSELR unsigned int
current effective value of CSSELR.

ArchMsg.Warning.warning_change_to_ns_when_tge_set

Attempting to change NS to 1 when HCR.TGE = 1.

ArchMsg.Warning.warning_contiguous_bit_check_abort

An abort occurred whilst attempting to check TLB entry is contiguous at %{ENTRY_ADDR}. Fields:

ENTRY_ADDR unsigned int
address of conflicting TLB entry.

ArchMsg.Warning.warning_contiguous_bit_error

TLB entry at %{ENTRY_ADDR} was not contiguous with entry at %{CONTIG_ADDR} Contents are %{ENTRY_DATA} but expected %{CONTIG_DATA}. Fields:

ENTRY_ADDR unsigned int
address of conflicting TLB entry.
ENTRY_DATA unsigned int
contents of conflicting TLB entry.
CONTIG_ADDR unsigned int
address of the TLB first read, with which this entry is expected to be contiguous.
CONTIG_DATA unsigned int
expected contents based on the entry at CONTIG_ADDR.

ArchMsg.Warning.warning_cp10_cp11_mismatch

Unpredictable configuration of CP10 and CP11 controls at EL%{EL:d}. Fields:

EL unsigned int
EL owning the control.

ArchMsg.Warning.warning_cp10_cp11_reserved_value

Unpredictable configuration of CPACR CP10 (%{CP10}) or CP11 (%{CP11}). Fields:

CP10 unsigned int
CP10 access.
CP11 unsigned int
CP11 access.

ArchMsg.Warning.warning_csselr_level_out_of_range

CSSELR.Level out of range, written value %{LEVEL} with only %{IMPLEMENTED:d} levels implemented. Fields:

LEVEL unsigned int
written value of CSSELR.Level.
IMPLEMENTED unsigned int
number of cache levels implemented.

ArchMsg.Warning.warning_debug_flow_control_bits_not_obeyed

Flow control bits for %{REGISTER} were not obeyed, causing %{ERROR}. Fields:

REGISTER enum
register under consideration.
0x0
DTRRX
0x1
DTRTX
0x2
ITR
ERROR enum
type of error resulting.
0x0
overflow
0x1
underflow

ArchMsg.Warning.warning_debug_register_access_during_reset

Unpredictable %{IS_WRITE:(read|write)} access to debug register offset %{OFFSET} during reset. Fields:

IS_WRITE unsigned int
Write Not Read.
OFFSET unsigned int
Register Offset.

ArchMsg.Warning.warning_decode_cps_inconsistent_fields

The mode setting fields in the CPS instruction are inconsistent.

ArchMsg.Warning.warning_decode_invalid_state

Instruction is unpredictable in current exception-level/security state.

ArchMsg.Warning.warning_default_cacheable_mmu_on

Default cacheable is enabled (HCR.DC = 1) while MMU is enabled.

ArchMsg.Warning.warning_default_cacheable_vmmu_off

Default cacheable is enabled (HCR.DC = 1) while HCR.VM = 0.

ArchMsg.Warning.warning_deprecated_wvr_bit_2_set

DBGWVR%{N:d}_EL1=%{WVR:h} has bit 2 set, deprecated in ARMv8. Fields:

N unsigned int
index.
WVR unsigned int
DBGWVR.

ArchMsg.Warning.warning_eret_while_software_step_active_pending

Missing ISB between setting MDSCR_EL1.SS and ERET.

ArchMsg.Warning.warning_exclusive_to_non_normal

Exclusive Access to Non-Normal Memory %{ADDR}. Fields:

ADDR unsigned int
Address.

ArchMsg.Warning.warning_exclusive_to_non_writeback

Exclusive Access to Non-Writeback-Cacheable Memory %{ADDR}. Fields:

ADDR unsigned int
Address.

ArchMsg.Warning.warning_execute_from_device_memory

An attempt was made to execute from Device memory.

ArchMsg.Warning.warning_illegal_cpsr_mode

Writing an illegal or unimplement mode (%{NEW_MODE:h}) to CPSR was unpredictable. Fields:

NEW_MODE unsigned int
New value of CPSR.M.

ArchMsg.Warning.warning_illegal_srs_mode

Illegal or UNPREDICTABLE mode (%{MODE:h}) used for SRS instruction. Fields:

MODE unsigned int
mode for Banked SP.

ArchMsg.Warning.warning_implementation_defined_read_debug_register_in_SCS

Read Access to Debug registers from the processor is IMPLEMENTATION DEFINED. Fields:

PPB_OFFSET unsigned int
debug register offset.

ArchMsg.Warning.warning_implementation_defined_sequential_security_transitions_supported

The behavior of a sequential instruction fetches that cross from non-secure to secure memory and contain SG instruction is CONSTRAINED UNPREDICTABLE.

ArchMsg.Warning.warning_implementation_defined_stack_limit_check_supported

It is IMPLEMENTATION DEFINED whether stack pointer limit checking is performed for the this instructions. Fields:

ADDRESS unsigned int
Address of instruction.
OPCODE unsigned int
instruction opcode.

ArchMsg.Warning.warning_implementation_defined_write_debug_register_in_SCS

Write Access to Debug registers from the processor is IMPLEMENTATION DEFINED. Fields:

PPB_OFFSET unsigned int
debug register offset.
DATA unsigned int
data attempted to be written.

ArchMsg.Warning.warning_invalid_tcr_granule

TCR.TG%{TG_ID:(0|1)} bits have been set to a granule size %{REQUEST:d}K not implemented - using %{SUBSTITUTE:d}K. Fields:

REQUEST signed int
page size requested (or 0 for reserved).
TG_ID bool
bits TG0 or TG1.
SUBSTITUTE signed int
best guess available page size.

ArchMsg.Warning.warning_load_multiple_user_registers_from_user_mode

An LDM(user registers) instruction executed from user mode.

ArchMsg.Warning.warning_load_pc_from_unaligned

PC loaded from an unaligned location.

ArchMsg.Warning.warning_reserved_breakpoint_state_match

%{IS_BREAKPOINT:(Watchpoint|Breakpoint)} programmed with a reserved combination of HMC, SSC and %{IS_BREAKPOINT:(PAC|PMC)}. Fields:

IS_BREAKPOINT unsigned int
Is breakpoint, not watchpoint.

ArchMsg.Warning.warning_shareability

Unpredictable: combination of the 1st and 2nd stages of translation is Normal Inner Non-Cacheable, Outer Non-Cacheable.

ArchMsg.Warning.warning_software_step_set_while_enabled

MDSCR_EL1.SS set to 1 while software step debug exceptions are enabled.

ArchMsg.Warning.warning_thumb_instruction_wraps_around_memory

Thumb instruction wraps around memory.

ArchMsg.Warning.warning_ttbr_sbz_bits_are_not_zero

%{TTBR}[%{MSB:d}:0] should be zero, but are not. Fields:

TTBR enum
which TTBR register.
0x0
TTBR0
0x1
TTBR1
0x2
VTTBR
0x3
TTBCR
0x4
VTCR
0x10
TTBR0_ELx
0x11
TTBR1_ELx
0x12
VTTBR_EL2
0x13
TCR_ELx
0x14
VTCR_EL2
MSB unsigned int
x-1.

ArchMsg.Warning.warning_unaligned_address_dbgdtrrx_write

Unaligned address %{ADDR} in X0/R0 when DBGDTRRX written in memory access mode. Fields:

ADDR unsigned int
Address.

ArchMsg.Warning.warning_unaligned_address_dbgdtrtx_read

Unaligned address %{ADDR} in X0/R0 when DBGDTRTX read in memory access mode. Fields:

ADDR unsigned int
Address.

ArchMsg.Warning.warning_unaligned_to_device

Unaligned Access to Device Memory %{ADDR}. Fields:

ADDR unsigned int
Address.

ArchMsg.Warning.warning_unaligned_to_strongly_ordered

Unaligned Access to Strongly Ordered Memory %{ADDR}. Fields:

ADDR unsigned int
Address.

ArchMsg.Warning.warning_unknown_sau_rnr

SAU_RNR was set to an unsupported value.

ArchMsg.Warning.warning_unpredictable_AIRCR_PRIP_and_BFHFNMINP

The effect of setting both AIRCR.BFHFNMINP and AIRCR.PRIP to 1 is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_VECTCLRACTIVE_when_not_in_debug

The effect of writing a 1 to AIRCR.VECTCLRACTIVE if the processor is not halted in Debug state is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_VECTRESET_and_SYSRESETREQ

When the processor is halted in Debug state, if a write to the register writes a 1 to both VECTRESET and SYSRESETREQ, the behavior is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_VECTRESET_when_not_in_debug

The effect of writing a 1 to AIRCR.VECTRESET if the processor is not halted in Debug state is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_incorrect_VKEY

The value 0x05FA must be written to AIRCR.VKEY, otherwise the register write is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_EXE_RETURN_Reserved_Bit

EXC_RETURN[23:7] are reserved with the special condition that all bits should be written as one. Values other than all 1s are UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_change_to_DEMCR_MON_STEP_at_insufficient_priority

The effect of changing DEMCR.MON_STEP at an execution priority that is lower than the priority of the DebugMonitor exception is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_change_to_priority_of_active_exception

Changing the priority of an active exception is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_clear_lspact

UNPREDICTABLE state on context switch. Fields:

DRVEXC_TAKEN unsigned int
derived exception taken not pended.
REACHED_LAST_STORE unsigned int
only the last faulted.

ArchMsg.Warning.warning_unpredictable_exception_catch

Generation of an exception catch event is unpredictable.

ArchMsg.Warning.warning_unpredictable_exception_return_inconsistent_state

State on exception return is unpredictable.

ArchMsg.Warning.warning_unpredictable_exception_return_instruction

Exception return instruction is unpredictable.

ArchMsg.Warning.warning_unpredictable_in_debug_state

Instruction is UNPREDICTABLE when executed in debug state.

ArchMsg.Warning.warning_unpredictable_pmu_counter_access

Access to PMU counters from non-secure EL0 or EL1 is UNPREDICTABLE with MDCR_EL2.HPMN set to 0.

ArchMsg.Warning.warning_unpredictable_prioritization_breakpoint_match_vector_catch

Two events with the same priority occurred at the same instruction: Address Matching Vector Catch debug event, and Breakpoint debug event It is constrained unpredictable which is taken.

ArchMsg.Warning.warning_unpredictable_stack_selection

UNPREDICTABLE state on context switch.

ArchMsg.Warning.warning_unpredictable_tsize_out_of_range

%{TCR}.T%{TTBR:d}SZ (%{TSIZE:d} bits) is out of range. Must be between 25 and %{TSIZE_MAX:d}. Fields:

TCR enum
Which TCR.
0x0
TTBR0
0x1
TTBR1
0x2
VTTBR
0x3
TTBCR
0x4
VTCR
0x10
TTBR0_ELx
0x11
TTBR1_ELx
0x12
VTTBR_EL2
0x13
TCR_ELx
0x14
VTCR_EL2
TTBR unsigned int
Which TTBR region.
TSIZE signed int
Value of TSize.
TSIZE_MAX signed int
The maximum allowed value.

ArchMsg.Warning.warning_unpredictable_unaligned_pc_as_base_register

The PC value must be word-aligned, otherwise the behavior of the instruction is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_vmsa_memattrib

Unpredictable vmsa memory attribute with texcb value programmed to %{TEXCB} when tex remap is %{TEX_REMAP}. Fields:

TEXCB unsigned int
texcb value.
TEX_REMAP bool
use tex remap.

ArchMsg.Warning.warning_unpredictable_vtcr_t0sz_sl0

The combination of VTCR.T0SZ=%{T0SZ:d} and VTCR.SL0=%{SL0:d} is unpredictable. Fields:

T0SZ signed int
VTCR.T0SZ, required input address range.
SL0 signed int
VTCR.SL0, starting level for stage 2 translation table walks.

ArchMsg.Warning.warning_unpredictable_write_DHCSR

UNPREDICTABLE set of bit-changes in DHCSR. Fields:

OLD unsigned int
previous value.
NEW unsigned int
data attempted to be written.

ArchMsg.Warning.warning_unsupported_access_to_memory_mapped_register

Access to memory mapped register is unsupported.

ArchMsg.Warning.warning_user_jmcr_access

User %{WRITE:(write|read)} access to JMCR is unpredictable. Fields:

WRITE unsigned int
access is write.

ArchMsg.Warning.warning_virt_ext_secure_privileged_access

Access to Virtualization Extensions from a non-Monitor Secure Privileged mode.

ArchMsg.Warning.warning_wcr_mask_and_bas

DBGWCR_EL1.MASK is non-zero and BAS is not 0xff.

ArchMsg.Warning.warning_wcr_mask_reserved

DBGWCR_ELn.MASK is set to a reserved value.

ArchMsg.Warning.warning_wcr_non_configuous_bas

DBGWCR_EL1.BAS has non-contiguous set of ones.

ArchMsg.Warning.warning_wvr_masked_bit_not_zero

DBGWVRn_EL1.VA contains a bit masked by DBGWCRn_EL1.MASK that is not zero.

ArchMsg.Why.why_illegal_state

Illegal mode change: %{MESSAGE}. Fields:

MESSAGE string
The message.

BRA_DIR

Direct branches, to immediate address. Fields:

PC unsigned int
The address of the branch instruction.
ISET enum
The instructions set of the branch instruction.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
TARGET_PC unsigned int
The address the instruction branches to.
TARGET_ISET enum
The instructions set after the branch.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
IS_COND bool
Indicates if this is a conditional branch.
CORE_NUM unsigned int
Core number in a multi processor.

BRA_INDIR

Indirect branches, perhaps to a register. Fields:

PC unsigned int
The address of the branch instruction.
ISET enum
The instructions set of the branch instruction.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
TARGET_PC unsigned int
The address the instruction branches to.
TARGET_ISET enum
The instructions set after the branch.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
IS_COND bool
Indicates if this is a conditional branch.
CORE_NUM unsigned int
Core number in a multi processor.

CACHE_MAINTENANCE_OP

Cache Maintenance Operation. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
SIDE enum
Inst / Data.
0x0
Instruction
0x1
Data
0x2
Instruction and Data
FUNCTION enum
Clean / Invalidate.
0x0
Clean
0x1
Invalidate
0x2
Clean and Invalidate
SCOPE enum
Affected region.
0x0
By Set/Way
0x1
By MVA to PoC
0x2
By MVA to PoU
0x3
All to PoU
0x4
All Inner Shareable to PoU
DATA unsigned int
Specified MVA or Set/way.

CCFAIL

Conditional instruction condition check fail. Fields:

COND enum
The condition of the conditional instruction.
0x0
EQ
0x1
NE
0x2
CS
0x3
CC
0x4
MI
0x5
PL
0x6
VS
0x7
VC
0x8
HI
0x9
LS
0xa
GE
0xb
LT
0xc
GT
0xd
LE
0xe
AL
PC unsigned int
The address of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.

CCFAIL_UNC

Conditional instruction condition check fail. Fields:

COND enum
The condition of the conditional instruction.
0x0
EQ
0x1
NE
0x2
CS
0x3
CC
0x4
MI
0x5
PL
0x6
VS
0x7
VC
0x8
HI
0x9
LS
0xa
GE
0xb
LT
0xc
GT
0xd
LE
0xe
AL
PC unsigned int
The address of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.

CCPASS

Conditional instruction condition check pass. Fields:

COND enum
The condition of the conditional instruction.
0x0
EQ
0x1
NE
0x2
CS
0x3
CC
0x4
MI
0x5
PL
0x6
VS
0x7
VC
0x8
HI
0x9
LS
0xa
GE
0xb
LT
0xc
GT
0xd
LE
0xe
AL
PC unsigned int
The address of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.

CCPASS_UNC

Conditional instruction condition check pass. Fields:

COND enum
The condition of the conditional instruction.
0x0
EQ
0x1
NE
0x2
CS
0x3
CC
0x4
MI
0x5
PL
0x6
VS
0x7
VC
0x8
HI
0x9
LS
0xa
GE
0xb
LT
0xc
GT
0xd
LE
0xe
AL
PC unsigned int
The address of the conditional instruction.
CORE_NUM unsigned int
Core number in a multi processor.

CHECKPOINT_MESSAGE

Report error messages from the checkpointing process. Fields:

message string
Message contents.

CHECKPOINT_RESTORE_END

Checkpoint restore completed.

CHECKPOINT_RESTORE_START

Checkpoint restore about to start.

CHECKPOINT_SAVE_END

Checkpoint save completed.

CHECKPOINT_SAVE_START

Checkpoint save about to start.

CODE_CACHE_FLUSH

Code cache flushed.

CODE_CACHE_FULL

Code cache full.

COMPILE_BLOCK_END

Last instruction of basic block translated. Fields:

VADDR unsigned int
Address of next instruction after this basic block.

COMPILE_BLOCK_START

First instruction of basic block translated. Fields:

VADDR unsigned int
Address of first instruction in basic block.

COMPILE_INST

ARM instruction compiled. Fields:

PC unsigned int
The address of the instruction.
OPCODE unsigned int
The opcode of the instruction.
SIZE unsigned int
The size of the instruction in bytes.
ISET enum
The instruction set of this instruction.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
ITSTATE unsigned int
The ITSTATE current for the instruction.
DISASS string
Disassembly of the instruction.

CONTEXTIDR

Context ID Register write. Fields:

NS bool
Secure or non-secure banked register is accessed.
VALUE unsigned int
The new value written.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.

CORE_ENDIAN

Core BE8 Big-Endian state changed. Fields:

BE8 bool
Core BE8 Big-Endian state.

CORE_INFO

Static processor attributes. Only triggered by a call to DumpState(). Fields:

NUM_CORES unsigned int
The number of cores in this MP processor.
CORE_NUM unsigned int
The number of this core in an MP processor.
CLUSTER_ID unsigned int
The cluster ID of this processor.
ARCH_PROFILE enum
The architecture profile of the core.
0x0
AR
0x1
M
0x2
A64
MEM_ARCH enum
The memory architecture of the core.
0x0
VMSA
0x1
PMSA
0x2
FLAT
QUANTUM_SIZE unsigned int
The default quantum size of the core.
SECURITY_FEATURES bool
Does the core have security features?
FPU_VERSION unsigned int
The VFP version implemented by the core.

CORE_LOADS

Processor load accesses. Fields:

VADDR unsigned int
The virtual address of the access.
RESPONSE enum
0=Aborted, 1=OK, 2=Exclusive Failed.
0x0
Aborted
0x1
OK
0x2
Failed
LOCK enum
Normal, exclusive or locked access.
0x0
Normal
0x1
Exclusive
0x2
Locked
TRANS bool
Is this a translated access.
ACQREL enum
Is this an acquire/release.
0x0
None
0x1
Global
0x2
Local
SIZE unsigned int
Width of the access in bytes. Only required if DATA is not traced.
ELEMENT_SIZE unsigned int
Width of each element.
PADDR unsigned int
The physical (translated) address.
NSDESC unsigned int
The physical address non-secure bit.
PADDR2 unsigned int
If different from PADDR, the physical address of the second page of the access.
NSDESC2 unsigned int
The second page physical address non-secure bit.
DATA unsigned int
The data read or written.

CORE_REGS

Changes of the core registers R0 to R14. Fields:

ID unsigned int
The register number, 0 to 14.
PHYS_ID enum
The physical register accessed.
0x0
R0_usr
0x1
R1_usr
0x2
R2_usr
0x3
R3_usr
0x4
R4_usr
0x5
R5_usr
0x6
R6_usr
0x7
R7_usr
0x8
R8_usr
0x9
R9_usr
0xa
R10_usr
0xb
R11_usr
0xc
R12_usr
0xd
SP_usr
0xe
LR_usr
0xf
R8_fiq
0x10
R9_fiq
0x11
R10_fiq
0x12
R11_fiq
0x13
R12_fiq
0x14
SP_fiq
0x15
LR_fiq
0x16
SP_irq
0x17
LR_irq
0x18
SP_svc
0x19
LR_svc
0x1a
SP_abt
0x1b
LR_abt
0x1c
SP_und
0x1d
LR_und
0x1e
SP_hyp
0x1f
ELR_hyp
0x20
SP_mon
0x21
LR_mon
0x22
SPSR_fiq
0x23
SPSR_irq
0x24
SPSR_svc
0x25
SPSR_und
0x26
SPSR_abt
0x27
SPSR_hyp
0x28
SPSR_mon
VALUE unsigned int
The new value written to the register.
OLD_VALUE unsigned int
The old value overwritten.
MODE enum
Bank of the register accessed.
0x0
EL0t
0x4
EL1t
0x5
EL1h
0x8
EL2t
0x9
EL2h
0xc
EL3t
0xd
EL3h
0x10
usr
0x11
fiq
0x12
irq
0x13
svc
0x16
mon
0x17
abt
0x1a
hyp
0x1b
und
0x1f
sys
CORE_NUM unsigned int
Core number in a multi processor.

CORE_REGS64

Changes of the core registers X0.X30, SP_ELn. Fields:

ID enum
The register number, 0.30 for X0.X30, >=32 for SP_ELn.
0x0
X0
0x1
X1
0x2
X2
0x3
X3
0x4
X4
0x5
X5
0x6
X6
0x7
X7
0x8
X8
0x9
X9
0xa
X10
0xb
X11
0xc
X12
0xd
X13
0xe
X14
0xf
X15
0x10
X16
0x11
X17
0x12
X18
0x13
X19
0x14
X20
0x15
X21
0x16
X22
0x17
X23
0x18
X24
0x19
X25
0x1a
X26
0x1b
X27
0x1c
X28
0x1d
X29
0x1e
X30
0x20
SP_EL0
0x21
SP_EL1
0x22
SP_EL2
0x23
SP_EL3
VALUE unsigned int
The new value written to the register.
OLD_VALUE unsigned int
The old value overwritten.
CORE_NUM unsigned int
Core number in a multi processor.

CORE_STORES

Processor store accesses. Fields:

VADDR unsigned int
The virtual address of the access.
RESPONSE enum
0=Aborted, 1=OK, 2=Exclusive Failed.
0x0
Aborted
0x1
OK
0x2
Failed
LOCK enum
Normal, exclusive or locked access.
0x0
Normal
0x1
Exclusive
0x2
Locked
TRANS bool
Is this a translated access.
ACQREL enum
Is this an acquire/release.
0x0
None
0x1
Global
0x2
Local
SIZE unsigned int
Width of the access in bytes. Only required if DATA is not traced.
ELEMENT_SIZE unsigned int
Width of each element.
PADDR unsigned int
The physical (translated) address.
NSDESC unsigned int
The physical address non-secure bit.
PADDR2 unsigned int
If different from PADDR, the physical address of the second page of the access.
NSDESC2 unsigned int
The second page physical address non-secure bit.
DATA unsigned int
The data read or written.

CP14_READ

System Coprocessor register read. Fields:

CRn unsigned int
CRn.
opc1 unsigned int
opcode 1.
CRm unsigned int
CRm.
opc2 unsigned int
opcode 2.
NS bool
Secure or non-secure banked register is accessed.
VALUE unsigned int
The value read.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the CP14 register accessed.

CP14_WRITE

System Coprocessor register write. Fields:

CRn unsigned int
CRn.
opc1 unsigned int
opcode 1.
CRm unsigned int
CRm.
opc2 unsigned int
opcode 2.
NS bool
Secure or non-secure banked register is accessed.
VALUE unsigned int
The new value written.
UPDATED_VALUE unsigned int
Updated value of the register now it has been written.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the CP14 register accessed.

CP15_READ

System Coprocessor register read. Fields:

CRn unsigned int
CRn.
opc1 unsigned int
opcode 1.
CRm unsigned int
CRm.
opc2 unsigned int
opcode 2.
NS bool
Secure or non-secure banked register is accessed.
VALUE unsigned int
The value read.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the CP15 register accessed.

CP15_READ64

System Coprocessor register read. Fields:

CRm unsigned int
CRm.
opc unsigned int
opcode 1.
NS bool
Secure or non-secure banked register is accessed.
VALUE unsigned int
The value read.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the CP15 register accessed.

CP15_WRITE

System Control Coprocessor register write. Fields:

CRn unsigned int
CRn.
opc1 unsigned int
opcode 1.
CRm unsigned int
CRm.
opc2 unsigned int
opcode 2.
NS bool
Secure or non-secure banked register is accessed.
VALUE unsigned int
The new value written.
UPDATED_VALUE unsigned int
Updated value of the register now it has been written.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the CP15 register accessed.

CP15_WRITE64

System Coprocessor register write. Fields:

CRm unsigned int
CRm.
opc unsigned int
opcode 1.
NS bool
Secure or non-secure banked register is accessed.
VALUE unsigned int
The new value written.
UPDATED_VALUE unsigned int
Updated value of the register now it has been written.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the CP15 register accessed.

CPSR

CPSR change. Fields:

VALUE unsigned int
The new CPSR value.
OLD_VALUE unsigned int
The old CPSR value.
CORE_NUM unsigned int
Core number in a multi processor.
UNKNOWN unsigned int
Bits within the register that have unknown value.

CRYPTO_SPEC

Every crypto instruction speculatively executed.

DEBUG_EVENT

Hardware debug support event. Fields:

EVENT enum
Description of event.
0x0
HaltingDebugState
0x1
HitWatchPoint
0x2
HitBreakPoint
0x3
HitVectorCatch
0x4
DBGEN
0x5
EDBGREQ
0x6
SPIDEN
0x7
NIDEN
0x8
PIDEN
0x9
PNIDEN
0xa
SPNIDEN
0xb
PADDRDBG31
0xc
DBGSWENABLE
0xd
DBGRESTART
0xe
HIDEN
0xf
HNIDEN
0x10
HitExceptionCatch
VALUE unsigned int
data value.

END_COMPILE

Compilation end. Fields:

INST_COUNT unsigned int
Number of instructions compiled since START_COMPILE.
FETCHFAIL_COUNT unsigned int
Number of basic blocks exited due to fetch failure START_COMPILE.
END_OF_PAGE_COUNT unsigned int
Number of basic blocks exited due to page boundary since START_COMPILE.
PAGE_STRADDLE_COUNT unsigned int
Number of basic blocks exited due to unaligned instructions crossing page since START_COMPILE.
NONSEQ_COUNT unsigned int
Number of basic blocks exited due to non-sequential instructions since START_COMPILE.

EXCEPTION

Exception taken. Fields:

PC unsigned int
The location where the exception occurred.
LR unsigned int
The value assigned to the link register.
PREFERRED_RETURN unsigned int
The preferred return address for the exception.
TARGET_PC unsigned int
The address the exception branches to.
VECTOR enum
The exception vector.
0x0
Reset
0x4
UndefinedInstr
0x8
SWI
0xc
PrefetchAbort
0x10
handleDataAbort
0x14
Hyp
0x18
IRQ
0x1c
FIQ
0x80
CURRENT_SP0_SYNC
0x81
CURRENT_SP0_IRQ
0x82
CURRENT_SP0_FIQ
0x83
CURRENT_SP0_ABORT
0x84
CURRENT_SPx_SYNC
0x85
CURRENT_SPx_IRQ
0x86
CURRENT_SPx_FIQ
0x87
CURRENT_SPx_ABORT
0x88
LOWER_64_SYNC
0x89
LOWER_64_IRQ
0x8a
LOWER_64_FIQ
0x8b
LOWER_64_ABORT
0x8c
LOWER_32_SYNC
0x8d
LOWER_32_IRQ
0x8e
LOWER_32_FIQ
0x8f
LOWER_32_ABORT
0xf8
Thumb2EE Check Array
0xfc
Thumb2EE Null Check
TARGET_ISET enum
The instruction set of the exception handler code.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
CORE_NUM unsigned int
Core number in a multi processor.
IS_PHYSICAL bool
Physical or Virtual exception.

EXCEPTION_END

Every exception completed.

EXCEPTION_RAISE

Every exception raised.

EXCEPTION_RETURN

Branches on leaving exception. Fields:

PC unsigned int
The address of the branch instruction.
ISET enum
The instructions set of the branch instruction.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
TARGET_PC unsigned int
The address the instruction branches to.
TARGET_ISET enum
The instructions set after the branch.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
IS_COND bool
Indicates if this is a conditional branch.
CORE_NUM unsigned int
Core number in a multi processor.

EXCEPTION_START

Every exception started.

EXTERNAL_END

External input-change completed.

EXTERNAL_START

External input-change started.

FIQ_TAKEN

FIQ taken exception.

INST

Every instruction executed. Fields:

PC unsigned int
The address of the instruction.
OPCODE unsigned int
The opcode of the instruction.
SIZE unsigned int
The size of the instruction in bytes.
MODE enum
The mode the core is in.
0x0
EL0t
0x4
EL1t
0x5
EL1h
0x8
EL2t
0x9
EL2h
0xc
EL3t
0xd
EL3h
0x10
usr
0x11
fiq
0x12
irq
0x13
svc
0x16
mon
0x17
abt
0x1a
hyp
0x1b
und
0x1f
sys
ISET enum
The current instruction set.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
PADDR unsigned int
The physical address of the instruction.
NSDESC unsigned int
The physical address non-secure bit.
PADDR2 unsigned int
If different from PADDR, the physical address of the second page of the instruction.
NSDESC2 unsigned int
The second page physical address non-secure bit.
NS unsigned int
The core's non-secure bit.
ITSTATE unsigned int
The current ITSTATE.
INST_COUNT unsigned int
The core's instruction counter, starting at 1 for the first instruction.
LOCAL_TIME unsigned int
The core's local time.
CORE_NUM unsigned int
Core number in a multi processor.
DISASS string
Disassembly of instruction.

INST_END

Every instruction completed.

INST_START

Every instruction started. Fields:

PC unsigned int
The address of the conditional instruction.
MODE enum
The mode the core is in.
0x0
EL0t
0x4
EL1t
0x5
EL1h
0x8
EL2t
0x9
EL2h
0xc
EL3t
0xd
EL3h
0x10
usr
0x11
fiq
0x12
irq
0x13
svc
0x16
mon
0x17
abt
0x1a
hyp
0x1b
und
0x1f
sys
ISET enum
The current instruction set.
0x0
ARM
0x1
Thumb
0x2
Jazelle
0x4
AArch64
NS enum
The current Secure State.
0x0
SEC
0x1
N_SEC

IRQ_TAKEN

IRQ taken exception.

LOCAL_MONITOR

Local monitor activity. Fields:

State enum
State of the monitor (Open/Exclusive).
0x0
Open
0x1
Exclusive
PADDR unsigned int
Local Monitor Address.

MEMMAP_DEBUG_READ

Memory mapped reads to the debug registers. Fields:

ADDR unsigned int
address.
EXT bool
Whether access is from an external device (such as the DAP).
VALUE unsigned int
The value read.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the debug register accessed.

MEMMAP_DEBUG_WRITE

Memory mapped writes to the debug registers. Fields:

ADDR unsigned int
address.
EXT bool
Whether access is from an external device (such as the DAP).
VALUE unsigned int
The new value written.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.
REG_NAME string
Name of the debug register accessed.

MMU_TRANS

Address translation information. Fields:

CORE_NUM unsigned int
Core number in a multi processor.
SIDE enum
Inst / Data.
0x0
Inst
0x1
Data
ASID unsigned int
Address space identifier.
VMID unsigned int
Virtual machine identifier.
VADDR unsigned int
Virtual address of the access.
Hyp bool
Entry matches in Hyp state only.
nG enum
Flag indicating whether ASID will be matched.
0x0
Global
0x1
Non-Global
NSDESC enum
Is secure side supposed to access secure or non-secure memory.
0x0
Secure
0x1
NonSecure
PADDR unsigned int
Physical address of the access.
PAGESIZE unsigned int
Page size as log2(size).
MEMTYPE enum
Memory type.
0x0
Device-nGnRnE (StronglyOrdered)
0x1
Device-nGnRE (Device)
0x2
Device-nGRE
0x3
Device-GRE
0x4
Normal
OUTERCACHE_TYPE enum
Outer Caching scheme (NC/MB/WA).
0x0
NonCacheable
0x1
WriteThrough
0x2
WriteBack
OUTERCACHE_RA bool
Is the outer cache allocate on read.
OUTERCACHE_WA bool
Is the outer cache allocate on write.
OUTERCACHE_TRANSIENT bool
Is the outer write-through transient.
INNERCACHE_TYPE enum
Inner Caching scheme (NC/MB/WA).
0x0
NonCacheable
0x1
WriteThrough
0x2
WriteBack
INNERCACHE_RA bool
Is the inner cache allocate on read.
INNERCACHE_WA bool
Is the inner cache allocate on write.
INNERCACHE_TRANSIENT bool
Is the inner write-through transient.
SH enum
Shareability.
0x0
NonShareable
0x1
InnerShareable
0x2
OuterShareable

MMU_TTB_READ

This event is triggered by reads caused by a translation table walk. Fields:

SIDE enum
Inst / Data.
0x0
Inst
0x1
Data
LPAE bool
Is this for an LPAE translation.
STAGE unsigned int
Translation stage.
LEVEL unsigned int
Translation table level.
NSreq bool
Non secure request.
NSmem bool
Non secure memory access.
IPA unsigned int
For stage 1, the IPA of the read.
PADDR unsigned int
The physical address of the read.
DATA unsigned int
The data read.
ABORTED bool
Was the walk successful.

MMU_TTB_WRITE

This event is triggered by writes caused by a translation table walk. Fields:

SIDE enum
Inst / Data.
0x0
Inst
0x1
Data
LPAE bool
Is this for an LPAE translation.
STAGE unsigned int
Translation stage.
LEVEL unsigned int
Translation table level.
NSreq bool
Non secure request.
NSmem bool
Non secure memory access.
IPA unsigned int
For stage 1, the IPA of the write.
PADDR unsigned int
The physical address of the write.
DATA unsigned int
The data written.
ABORTED bool
Was the walk successful.

MODE_CHANGE

Mode change. Fields:

MODE enum
The new mode.
0x0
EL0t
0x4
EL1t
0x5
EL1h
0x8
EL2t
0x9
EL2h
0xc
EL3t
0xd
EL3h
0x10
usr
0x11
fiq
0x12
irq
0x13
svc
0x16
mon
0x17
abt
0x1a
hyp
0x1b
und
0x1f
sys
OLD_MODE enum
The old mode.
0x0
EL0t
0x4
EL1t
0x5
EL1h
0x8
EL2t
0x9
EL2h
0xc
EL3t
0xd
EL3h
0x10
usr
0x11
fiq
0x12
irq
0x13
svc
0x16
mon
0x17
abt
0x1a
hyp
0x1b
und
0x1f
sys
CORE_NUM unsigned int
Core number in a multi processor.
NON_SECURE enum
The new security state.
0x0
SECURE
0x1
NON_SECURE

PERIODIC

Called for every quantum. Fields:

INST_COUNT unsigned int
The instruction count of this CPU.
PC unsigned int
The address of the next instruction to be executed on this CPU.
CORE_NUM unsigned int
Core number in a multi processor.

PMU_COUNTER_OVERFLOW

PMU counter overflow. Fields:

INDEX unsigned int
Counter index (as selected by PMSELR).
EVENT_ID unsigned int
Event Identifier.
INTERRUPT bool
Is interrupt enabled on overflow for this counter.

PREFETCH_MEMORY64

Prefetch from PRFM or PRFUM instructions. Fields:

PRFOP unsigned int
Prefetch hint.
VADDR unsigned int
Virtual address of the location that should be prefetched.

PRELOAD_DATA

Data preload from PLD instruction. Fields:

VADDR unsigned int
Virtual address of the data that should be preloaded.

PRE_TTB_READ

This event is triggered before reads caused by a translation table walk. Fields:

ADDR unsigned int
The physical address of the read.

RUN_STATE

Run state transition. Fields:

INST_COUNT unsigned int
Ticks count at point of transition.
NEW enum
New run state.
0x0
UNKNOWN
0x1
RUNNING
0x2
HALTED
0x3
STANDBY_WFE
0x4
STANDBY_WFI
0x5
IN_RESET
0x6
DORMANT
0x7
SHUTDOWN
0x8
BARRIER_WAIT
OLD enum
Old run state.
0x0
UNKNOWN
0x1
RUNNING
0x2
HALTED
0x3
STANDBY_WFE
0x4
STANDBY_WFI
0x5
IN_RESET
0x6
DORMANT
0x7
SHUTDOWN
0x8
BARRIER_WAIT

SIGNAL

External signal state change. Fields:

SIGNAL enum
Signal that changed.
0x0
FIQ
0x1
IRQ
0x2
Reset
0x3
SystemError
0x4
Abort
0x5
Debug
0x6
Halt
0x7
OSUnlockCatch
0x8
VFIQ
0x9
VIRQ
0xa
POReset
0xb
SysPOReset
0xc
DebugReset
0xd
ResetHold
0xf
CP15SDisable
STATE bool
Signal asserted state.

SPSR

SPSR change. Fields:

VALUE unsigned int
The new SPSR value.
OLD_VALUE unsigned int
The old SPSR value.
MODE enum
Which of the banked SPSR registers is written.
0x0
EL0t
0x4
EL1t
0x5
EL1h
0x8
EL2t
0x9
EL2h
0xc
EL3t
0xd
EL3h
0x11
fiq
0x12
irq
0x13
svc
0x16
mon
0x17
abt
0x1a
hyp
0x1b
und
CORE_NUM unsigned int
Core number in a multi processor.

START_COMPILE

Compilation started. Fields:

VADDR unsigned int
Instruction where compilation begins.

SYNC

Called for every synchronization. Fields:

INST_COUNT unsigned int
The instruction count of this CPU.
LOCAL_TIME unsigned int
The local time of this CPU.
LOCAL_QUANTUM unsigned int
The local quantum of this CPU.
CORE_NUM unsigned int
Core number in a multi processor.

SYSCALL

System call instruction executed. Fields:

VADDR unsigned int
Instruction that caused the system call.
TYPE enum
System call type.
0x0
SVC
0x1
HVC
0x2
SMC
IMM unsigned int
Immediate value of the system call instruction.

SYSREG_READ64

System Coprocessor register read. Fields:

REGNUM enum
Internal register number.
0x4071
IC IALLUIS
0x4075
IC IALLU
0x4078
AT S1E1R
0x4083
TLBI VMALLE1IS
0x4087
TLBI VMALLE1
0x40b0-0x40bf 0x40f0-0x40f3
IMP DEF
0x40f4
RAMIDX
0x40f5-0x40ff
IMP DEF
0x4176
DC IVAC
0x4178
AT S1E1W
0x4183
TLBI VAE1IS
0x4187
TLBI VAE1
0x41b0-0x41bf 0x41f0-0x41ff
IMP DEF
0x4276
DC ISW
0x4278
AT S1E0R
0x427a
DC CSW
0x427e
DC CISW
0x4283
TLBI ASIDE1IS
0x4287
TLBI ASIDE1
0x42b0-0x42bf 0x42f0-0x42ff
IMP DEF
0x4378
AT S1E0W
0x4383
TLBI VAAE1IS
0x4387
TLBI VAAE1
0x43b0-0x43bf 0x43f0-0x43ff 0x44b0-0x44bf 0x44f0-0x44ff
IMP DEF
0x4583
TLBI VALE1IS
0x4587
TLBI VALE1
0x45b0-0x45bf 0x45f0-0x45ff 0x46b0-0x46bf 0x46f0-0x46ff
IMP DEF
0x4783
TLBI VAALE1IS
0x4787
TLBI VAALE1
0x47b0-0x47bf 0x47f0-0x47ff 0x48b0-0x48bf 0x48f0-0x48ff 0x49b0-0x49bf 0x49f0-0x49ff 0x4ab0-0x4abf 0x4af0-0x4aff 0x4bb0-0x4bbf 0x4bf0-0x4bff 0x4cb0-0x4cbf 0x4cf0-0x4cff 0x4db0-0x4dbf 0x4df0-0x4dff 0x4eb0-0x4ebf 0x4ef0-0x4eff 0x4fb0-0x4fbf 0x4ff0-0x4fff 0x50b0-0x50bf 0x50f0-0x50ff 0x51b0-0x51bf 0x51f0-0x51ff 0x52b0-0x52bf 0x52f0-0x52ff 0x53b0-0x53bf 0x53f0-0x53ff 0x54b0-0x54bf 0x54f0-0x54ff 0x55b0-0x55bf 0x55f0-0x55ff 0x56b0-0x56bf 0x56f0-0x56ff 0x57b0-0x57bf 0x57f0-0x57ff 0x58b0-0x58bf 0x58f0-0x58ff
IMP DEF
0x5974
DC ZVA
0x5975
IC IVAU
0x597a
DC CVAC
0x597b
DC CVAU
0x597e
DC CIVAC
0x59b0-0x59bf 0x59f0-0x59ff 0x5ab0-0x5abf 0x5af0-0x5aff 0x5bb0-0x5bbf 0x5bf0-0x5bff 0x5cb0-0x5cbf 0x5cf0-0x5cff 0x5db0-0x5dbf 0x5df0-0x5dff 0x5eb0-0x5ebf 0x5ef0-0x5eff 0x5fb0-0x5fbf 0x5ff0-0x5fff
IMP DEF
0x6078
AT S1E2R
0x6083
TLBI ALLE2IS
0x6087
TLBI ALLE2
0x60b0-0x60bf 0x60f0-0x60ff
IMP DEF
0x6178
AT S1E2W
0x6180
TLBI IPAS2E1IS
0x6183
TLBI VAE2IS
0x6184
TLBI IPAS2E1
0x6187
TLBI VAE2
0x61b0-0x61bf 0x61f0-0x61ff 0x62b0-0x62bf 0x62f0-0x62ff 0x63b0-0x63bf 0x63f0-0x63ff
IMP DEF
0x6478
AT S12E1R
0x6483
TLBI ALLE1IS
0x6487
TLBI ALLE1
0x64b0-0x64bf 0x64f0-0x64ff
IMP DEF
0x6578
AT S12E1W
0x6580
TLBI IPAS2LE1IS
0x6583
TLBI VALE2IS
0x6584
TLBI IPAS2LE1
0x6587
TLBI VALE2
0x65b0-0x65bf 0x65f0-0x65ff
IMP DEF
0x6678
AT S12E0R
0x6683
TLBI VMALLS12E1IS
0x6687
TLBI VMALLS12E1
0x66b0-0x66bf 0x66f0-0x66ff
IMP DEF
0x6778
AT S12E0W
0x67b0-0x67bf 0x67f0-0x67ff 0x68b0-0x68bf 0x68f0-0x68ff 0x69b0-0x69bf 0x69f0-0x69ff 0x6ab0-0x6abf 0x6af0-0x6aff 0x6bb0-0x6bbf 0x6bf0-0x6bff 0x6cb0-0x6cbf 0x6cf0-0x6cff 0x6db0-0x6dbf 0x6df0-0x6dff 0x6eb0-0x6ebf 0x6ef0-0x6eff 0x6fb0-0x6fbf 0x6ff0-0x6fff
IMP DEF
0x7078
AT S1E3R
0x7083
TLBI ALLE3IS
0x7087
TLBI ALLE3
0x70b0-0x70bf 0x70f0-0x70ff
IMP DEF
0x7178
AT S1E3W
0x7183
TLBI VAE3IS
0x7187
TLBI VAE3
0x71b0-0x71bf 0x71f0-0x71ff 0x72b0-0x72bf 0x72f0-0x72ff 0x73b0-0x73bf 0x73f0-0x73ff 0x74b0-0x74bf 0x74f0-0x74ff
IMP DEF
0x7583
TLBI VALE3IS
0x7587
TLBI VALE3
0x75b0-0x75bf 0x75f0-0x75ff 0x76b0-0x76bf 0x76f0-0x76ff 0x77b0-0x77bf 0x77f0-0x77ff 0x78b0-0x78bf 0x78f0-0x78ff 0x79b0-0x79bf 0x79f0-0x79ff 0x7ab0-0x7abf 0x7af0-0x7aff 0x7bb0-0x7bbf 0x7bf0-0x7bff 0x7cb0-0x7cbf 0x7cf0-0x7cff 0x7db0-0x7dbf 0x7df0-0x7dff 0x7eb0-0x7ebf 0x7ef0-0x7eff 0x7fb0-0x7fbf 0x7ff0-0x7fff
IMP DEF
0x8002
MDCCINT_EL1
0x8010
MDRAR_EL1
0x8200
OSDTRRX_EL1
0x8202
MDSCR_EL1
0x8203
OSDTRTX_EL1
0x8206
OSECCR_EL1
0x8400
DBGBVR0_EL1
0x8401
DBGBVR1_EL1
0x8402
DBGBVR2_EL1
0x8403
DBGBVR3_EL1
0x8404
DBGBVR4_EL1
0x8405
DBGBVR5_EL1
0x8410
OSLAR_EL1
0x8411
OSLSR_EL1
0x8413
OSDLR_EL1
0x8414
DBGPRCR_EL1
0x8500
DBGBCR0_EL1
0x8501
DBGBCR1_EL1
0x8502
DBGBCR2_EL1
0x8503
DBGBCR3_EL1
0x8504
DBGBCR4_EL1
0x8505
DBGBCR5_EL1
0x8600
DBGWVR0_EL1
0x8601
DBGWVR1_EL1
0x8602
DBGWVR2_EL1
0x8603
DBGWVR3_EL1
0x8678
DBGCLAIMSET_EL1
0x8679
DBGCLAIMCLR_EL1
0x867e
DBGAUTHSTATUS_EL1
0x8700
DBGWCR0_EL1
0x8701
DBGWCR1_EL1
0x8702
DBGWCR2_EL1
0x8703
DBGWCR3_EL1
0x9801
MDCCSR_EL0
0x9804
DBGDTR_EL0
0x9805
DBGDTRxX_EL0
0xa007
DBGVCR32_EL2
0xc000
MIDR_EL1
0xc001
ID_PFR0_EL1
0xc002
ID_ISAR0_EL1
0xc003
MVFR0_EL1
0xc004
ID_AA64PFR0_EL1
0xc005
ID_AA64DFR0_EL1
0xc006
ID_AA64ISAR0_EL1
0xc007
ID_AA64MMFR0_EL1
0xc010
SCTLR_EL1
0xc020
TTBR0_EL1
0xc040
SPSR_EL1
0xc041
SP_EL0
0xc042
SPSel
0xc051
AFSR0_EL1
0xc052
ESR_EL1
0xc060
FAR_EL1
0xc074
PAR_EL1
0xc0a2
MAIR_EL1
0xc0a3
AMAIR_EL1
0xc0b0-0xc0bf
IMP DEF
0xc0c0
VBAR_EL1
0xc0c1
ISR_EL1
0xc0e1
CNTKCTL_EL1
0xc0f0-0xc0f1
IL1D0
0xc0f2-0xc0ff
IMP DEF
0xc101
ID_PFR1_EL1
0xc102
ID_ISAR1_EL1
0xc103
MVFR1_EL1
0xc104
ID_AA64PFR1_EL1
0xc105
ID_AA64DFR1_EL1
0xc106
ID_AA64ISAR1_EL1
0xc107
ID_AA64MMFR1_EL1
0xc110
ACTLR_EL1
0xc120
TTBR1_EL1
0xc140
ELR_EL1
0xc151
AFSR1_EL1
0xc19e
PMINTENSET_EL1
0xc1b0-0xc1bf
IMP DEF
0xc1d0
CONTEXTIDR_EL1
0xc1f0
IL1D1
0xc1f1
DL1D1
0xc1f2-0xc1ff
IMP DEF
0xc201
ID_DFR0_EL1
0xc202
ID_ISAR2_EL1
0xc203
MVFR2_EL1
0xc204-0xc207
Reserved
0xc210
CPACR_EL1
0xc220
TCR_EL1
0xc242
CURREL
0xc29e
PMINTENCLR_EL1
0xc2b0-0xc2bf
IMP DEF
0xc2f0
IL1D2
0xc2f1
DL1D2
0xc2f2-0xc2ff
IMP DEF
0xc301
ID_AFR0_EL1
0xc302
ID_ISAR3_EL1
0xc303-0xc307
Reserved
0xc342
PAN
0xc3b0-0xc3bf
IMP DEF
0xc3f0
IL1D3
0xc3f1
DL1D3
0xc3f2-0xc3ff
IMP DEF
0xc401
ID_MMFR0_EL1
0xc402
ID_ISAR4_EL1
0xc403-0xc404
Reserved
0xc405
ID_AA64AFR0_EL1
0xc406-0xc407
Reserved
0xc4b0-0xc4bf
IMP DEF
0xc4d0
TPIDR_EL1
0xc4f0
IMP DEF
0xc4f1
DL1D4
0xc4f2-0xc4ff
IMP DEF
0xc500
MPIDR_EL1
0xc501
ID_MMFR1_EL1
0xc502
ID_ISAR5_EL1
0xc503-0xc504
Reserved
0xc505
ID_AA64AFR1_EL1
0xc506-0xc507
Reserved
0xc5b0-0xc5bf 0xc5f0-0xc5ff
IMP DEF
0xc600
REVIDR_EL1
0xc601
ID_MMFR2_EL1
0xc602-0xc607
Reserved
0xc6b0-0xc6bf 0xc6f0-0xc6ff
IMP DEF
0xc701
ID_MMFR3_EL1
0xc702-0xc707
Reserved
0xc7b0-0xc7bf 0xc7f0-0xc7ff
IMP DEF
0xc800
CCSIDR_EL1
0xc8b0-0xc8bf
IMP DEF
0xc8f0
L2ACTLR
0xc8f1
IMP DEF
0xc8f2
CPUACTLR_EL1
0xc8f3
CBAR_EL1
0xc8f4-0xc8ff
IMP DEF
0xc900
CLIDR_EL1
0xc9b0-0xc9bf 0xc9f0-0xc9f1
IMP DEF
0xc9f2
CPUECTLR_EL1
0xc9f3-0xc9ff
IMP DEF
0xcab0
L2CTLR
0xcab1-0xcabf 0xcaf0-0xcaf1
IMP DEF
0xcaf2
CPUMERRSR_EL1
0xcaf3-0xcaff
IMP DEF
0xcbb0
L2ECTLR
0xcbb1-0xcbbf 0xcbf0-0xcbf1
IMP DEF
0xcbf2
L2MERRSR_EL1
0xcbf3-0xcbff 0xccb0-0xccbf 0xccf0-0xccff 0xcdb0-0xcdbf 0xcdf0-0xcdff 0xceb0-0xcebf 0xcef0-0xceff
IMP DEF
0xcf00
AIDR_EL1
0xcfb0-0xcfbf 0xcff0-0xcfff
IMP DEF
0xd000
CSSELR_EL1
0xd0b0-0xd0bf 0xd0f0-0xd0ff 0xd1b0-0xd1bf 0xd1f0-0xd1ff 0xd2b0-0xd2bf 0xd2f0-0xd2ff 0xd3b0-0xd3bf 0xd3f0-0xd3ff 0xd4b0-0xd4bf 0xd4f0-0xd4ff 0xd5b0-0xd5bf 0xd5f0-0xd5ff 0xd6b0-0xd6bf 0xd6f0-0xd6ff 0xd7b0-0xd7bf 0xd7f0-0xd7ff
IMP DEF
0xd842
NZCV
0xd844
FPCR
0xd845
DSPSR_EL0
0xd89c
PMCR_EL0
0xd89d
PMCCNTR_EL0
0xd89e
PMUSERENR_EL0
0xd8b0-0xd8bf
IMP DEF
0xd8e0
CNTFRQ_EL0
0xd8e2
CNTP_TVAL_EL0
0xd8e3
CNTV_TVAL_EL0
0xd8e8
PMEVCNTR0_EL0
0xd8ec
PMEVTYPER0_EL0
0xd8f0-0xd8ff
IMP DEF
0xd900
CTR_EL0
0xd942
DAIF
0xd944
FPSR
0xd945
DLR_EL0
0xd99c
PMCNTENSET_EL0
0xd99d
PMXEVTYPER_EL0
0xd9b0-0xd9bf
IMP DEF
0xd9e0
CNTPCT_EL0
0xd9e2
CNTP_CTL_EL0
0xd9e3
CNTV_CTL_EL0
0xd9e8
PMEVCNTR1_EL0
0xd9ec
PMEVTYPER1_EL0
0xd9f0-0xd9ff
IMP DEF
0xda9c
PMCNTENCLR_EL0
0xda9d
PMXEVCNTR_EL0
0xdab0-0xdabf
IMP DEF
0xdad0
TPIDR_EL0
0xdae0
CNTVCT_EL0
0xdae2
CNTP_CVAL_EL0
0xdae3
CNTV_CVAL_EL0
0xdae8
PMEVCNTR2_EL0
0xdaec
PMEVTYPER2_EL0
0xdaf0-0xdaff
IMP DEF
0xdb9c
PMOVSCLR_EL0
0xdb9e
PMOVSSET_EL0
0xdbb0-0xdbbf
IMP DEF
0xdbd0
TPIDRRO_EL0
0xdbe8
PMEVCNTR3_EL0
0xdbec
PMEVTYPER3_EL0
0xdbf0-0xdbff
IMP DEF
0xdc9c
PMSWINC_EL0
0xdcb0-0xdcbf
IMP DEF
0xdce8
PMEVCNTR4_EL0
0xdcec
PMEVTYPER4_EL0
0xdcf0-0xdcff
IMP DEF
0xdd9c
PMSELR_EL0
0xddb0-0xddbf
IMP DEF
0xdde8
PMEVCNTR5_EL0
0xddec
PMEVTYPER5_EL0
0xddf0-0xddff
IMP DEF
0xde9c
PMCEID0_EL0
0xdeb0-0xdebf 0xdef0-0xdeff
IMP DEF
0xdf00
DCZID_EL0
0xdf9c
PMCEID1_EL0
0xdfb0-0xdfbf
IMP DEF
0xdfef
PMCCFILTR_EL0
0xdff0-0xdfff
IMP DEF
0xe000
VPIDR_EL2
0xe010
SCTLR_EL2
0xe011
HCR_EL2
0xe020
TTBR0_EL2
0xe021
VTTBR_EL2
0xe030
DACR32_EL2
0xe040
SPSR_EL2
0xe041
SP_EL1
0xe043
SPSR_IRQ
0xe051
AFSR0_EL2
0xe052
ESR_EL2
0xe053
FPEXC32_EL2
0xe060
FAR_EL2
0xe0a2
MAIR_EL2
0xe0a3
AMAIR_EL2
0xe0b0-0xe0bf
IMP DEF
0xe0c0
VBAR_EL2
0xe0e1
CNTHCTL_EL2
0xe0e2
CNTHP_TVAL_EL2
0xe0f0-0xe0ff
IMP DEF
0xe110
ACTLR_EL2
0xe111
MDCR_EL2
0xe140
ELR_EL2
0xe143
SPSR_ABT
0xe150
IFSR32_EL2
0xe151
AFSR1_EL2
0xe1b0-0xe1bf
IMP DEF
0xe1e2
CNTHP_CTL_EL2
0xe1f0-0xe1ff
IMP DEF
0xe211
CPTR_EL2
0xe220
TCR_EL2
0xe221
VTCR_EL2
0xe243
SPSR_UND
0xe2b0-0xe2bf
IMP DEF
0xe2d0
TPIDR_EL2
0xe2e2
CNTHP_CVAL_EL2
0xe2f0-0xe2ff
IMP DEF
0xe311
HSTR_EL2
0xe343
SPSR_FIQ
0xe3b0-0xe3bf
IMP DEF
0xe3e0
CNTVOFF_EL2
0xe3f0-0xe3ff
IMP DEF
0xe460
HPFAR_EL2
0xe4b0-0xe4bf 0xe4f0-0xe4ff
IMP DEF
0xe500
VMPIDR_EL2
0xe5b0-0xe5bf 0xe5f0-0xe5ff 0xe6b0-0xe6bf 0xe6f0-0xe6ff
IMP DEF
0xe711
HACR_EL2
0xe7b0-0xe7bf 0xe7f0-0xe7ff 0xe8b0-0xe8bf 0xe8f0-0xe8ff 0xe9b0-0xe9bf 0xe9f0-0xe9ff 0xeab0-0xeabf 0xeaf0-0xeaff 0xebb0-0xebbf 0xebf0-0xebff 0xecb0-0xecbf 0xecf0-0xecff 0xedb0-0xedbf 0xedf0-0xedff 0xeeb0-0xeebf 0xeef0-0xeeff 0xefb0-0xefbf 0xeff0-0xefff
IMP DEF
0xf010
SCTLR_EL3
0xf011
SCR_EL3
0xf020
TTBR0_EL3
0xf040
SPSR_EL3
0xf041
SP_EL2
0xf051
AFSR0_EL3
0xf052
ESR_EL3
0xf060
FAR_EL3
0xf0a2
MAIR_EL3
0xf0a3
AMAIR_EL3
0xf0b0-0xf0bf
IMP DEF
0xf0c0
VBAR_EL3
0xf0f0-0xf0ff
IMP DEF
0xf110
ACTLR_EL3
0xf111
SDER32_EL3
0xf113
MDCR_EL3
0xf140
ELR_EL3
0xf151
AFSR1_EL3
0xf1b0-0xf1bf
IMP DEF
0xf1c0
RVBAR_EL3
0xf1f0-0xf1ff
IMP DEF
0xf211
CPTR_EL3
0xf220
TCR_EL3
0xf2b0-0xf2bf
IMP DEF
0xf2c0
RMR_EL3
0xf2d0
TPIDR_EL3
0xf2f0-0xf2ff 0xf3b0-0xf3bf 0xf3f0-0xf3ff 0xf4b0-0xf4bf 0xf4f0-0xf4ff 0xf5b0-0xf5bf 0xf5f0-0xf5ff 0xf6b0-0xf6bf 0xf6f0-0xf6ff 0xf7b0-0xf7bf 0xf7f0-0xf7ff 0xf8b0-0xf8bf
IMP DEF
0xf8e2
CNTPS_TVAL_EL1
0xf8f0-0xf8ff 0xf9b0-0xf9bf
IMP DEF
0xf9e2
CNTPS_CTL_EL1
0xf9f0-0xf9ff 0xfab0-0xfabf
IMP DEF
0xfae2
CNTPS_CVAL_EL1
0xfaf0-0xfaff 0xfbb0-0xfbbf 0xfbf0-0xfbff 0xfcb0-0xfcbf 0xfcf0-0xfcff 0xfdb0-0xfdbf 0xfdf0-0xfdff 0xfeb0-0xfebf 0xfef0-0xfeff 0xffb0-0xffbf 0xfff0-0xffff
IMP DEF
VALUE unsigned int
The value read.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.

SYSREG_UPDATE32

Triggers when the system updates a register. Fields:

REG enum
Register number.
0x0
SCR
0x1
NSACR
0x2
MVBAR
0x3
DFSR_S
0x4
DFAR_S
0x5
IFSR_S
0x6
IFAR_S
0x7
AIFSR_S
0x8
ADFSR_S
0x9
SCTLR_S
0xa
TPIDRURW_S
0xb
TPIDRUR0_S
0xc
TPIDRPRW_S
0xd
VBAR_S
0xe
ACTLR_S
0xf
DFSR_NS
0x10
DFAR_NS
0x11
IFSR_NS
0x12
IFAR_NS
0x13
AIFSR_NS
0x14
ADFSR_NS
0x15
SCTLR_NS
0x16
TPIDRURW_NS
0x17
TPIDRURO_NS
0x18
TPIDRPRW_NS
0x19
VBAR_NS
0x1a
ACTLR_NS
0x1b
ELR
0x1c
HCR
0x1d
HDCR
0x1e
HCPTR
0x1f
HSTR
0x20
HDFAR
0x21
HIFAR
0x22
HPFAR
0x23
HSCTLR
0x24
HSR
0x25
HTPIDR
0x26
HVBAR
0x27
VPIDR
0x28
VMPIDR
0x29
HCR2
0x2a
HACTLR
0x2b
MPIDR
0x2c
CPACR
0x2d
TEECR
0x2e
TEEHBR
0x2f
WFAR
0x30
ISR
0x31
SPSR_svc
0x32
SPSR_irq
0x33
SPSR_fiq
0x34
SPSR_abt
0x35
SPSR_und
0x36
SPSR_mon
0x37
SPSR_hyp
0x38
VDFSR
0x39
SDER
0x3a
CNTFRQ_EL0
0x3b
CNTKCTL_EL1
0x3c
CNTHCTL_EL2
0x3d
CNTPS_CTL_EL1
0x3e
CNTP_CTL_EL0
0x3f
CNTV_CTL_EL0
0x40
CNTHP_CTL_EL2
0x41
DBGDSCRint
0x42
DBGDSCRext
0x43
DBGDTRRXext
0x44
DBGDTRRXintorDBGDTRTXint
0x45
DBGDTRTXext
0x46
DBGWFAR
0x47
DBGVCR
0x48
EDECR
0x49
EDITR
0x4a
EDPCSRlo
0x4b
EDCIDSR
0x4c
EDVIDSR
0x4d
EDRCR
0x4e
DBGBVR0
0x4f
DBGBVR1
0x50
DBGBVR2
0x51
DBGBVR3
0x52
DBGBVR4
0x53
DBGBVR5
0x54
DBGBCR0
0x55
DBGBCR1
0x56
DBGBCR2
0x57
DBGBCR3
0x58
DBGBCR4
0x59
DBGBCR5
0x5a
DBGWVR0
0x5b
DBGWVR1
0x5c
DBGWVR2
0x5d
DBGWVR3
0x5e
DBGWCR0
0x5f
DBGWCR1
0x60
DBGWCR2
0x61
DBGWCR3
0x62
DBGDRAR
0x63
DBGDSAR
0x64
DBGOSLAR
0x65
OSLSR_EL1
0x66
EDPRCR
0x67
EDPRSR
0x68
MIDR
0x69
RESERVED (MIDR1)
0x6a
RESERVED (MIDR2)
0x6b
RESERVED (MIDR3)
0x6c
RESERVED (MIDR4)
0x6d
RESERVED (MIDR5)
0x6e
RESERVED (MIDR6)
0x6f
RESERVED (MIDR7)
0x70
ID_AA64PFR0[31:0]
0x71
ID_AA64PFR0[63:32]
0x72
ID_AA64DFR0[31:0]
0x73
ID_AA64DFR0[63:32]
0x74
ID_AA64ISAR0[31:0]
0x75
ID_AA64ISAR0[63:32]
0x76
ID_AA64MFR0[31:0]
0x77
ID_AA64MFR0[63:32]
0x78
ID_AA64PFR1[31:0]
0x79
ID_AA64PFR1[63:32]
0x7a
ID_AA64DFR1[31:0]
0x7b
ID_AA64DFR1[63:32]
0x7c
ID_AA64ISAR1[31:0]
0x7d
ID_AA64ISAR1[63:32]
0x7e
ID_AA64MMFR1[31:0]
0x7f
ID_AA64MMFR1[63:32]
0x80
DBGITCTRL
0x81
DBGCLAIMSET
0x82
DBGCLAIMCLR
0x83
EDLAR
0x84
EDLSR
0x85
DBGAUTHSTATUS
0x86
EDDEVTYPE
0x87
EDPID0
0x88
EDPID1
0x89
EDPID2
0x8a
EDPID3
0x8b
EDPID4
0x8c
RESERVED (EDPID5)
0x8d
RESERVED (EDPID6)
0x8e
RESERVED (EDPID7)
0x8f
EDCID0
0x90
EDCID1
0x91
EDCID2
0x92
EDCID3
0x93
TEECR
0x94
TEEHBR
0x95
DBGBXVR0
0x96
DBGBXVR1
0x97
DBGBXVR2
0x98
DBGBXVR3
0x99
DBGBXVR4
0x9a
DBGBXVR5
0x9b
DBGDIDR
0x9c
EDDEVID
0x9d
EDDEVID1
0x9e
EDDEVID2
0x9f
DBGOSDLR
0xa0
DBGOSSRR
0xa1
EDPCSRhi
0xa2
DCCINT
0xa3
EDESR
0xa4
EDWARlo
0xa5
EDWARhi
0xa6
EDACR
0xa7
EDECCR
0xa8
DBGWXVR0
0xa9
DBGWXVR1
0xaa
DBGWXVR2
0xab
DBGWXVR3
0xac
EDDEVAFF0
0xad
EDDEVAFF1
0xae
EDDEVARCH
0xaf
EDSCR
0xb0
MDCCSR_EL0
0xb1
MDSCR_EL1
0xb2
PMCID1SR
0xb3
PMVIDSR
0xb4
PMCID1SR
0xb5
PRRR_S
0xb6
NMRR_S
0xb7
DACR_S
0xb8
FCSE_S
0xb9
TTBCR_S
0xba
TTBR0_S
0xbb
TTBR1_S
0xbc
CONTEXTIDR_S
0xbd
PAR_S
0xbe
PRRR_NS
0xbf
NMRR_NS
0xc0
DACR_NS
0xc1
FCSE_NS
0xc2
TTBCR_NS
0xc3
TTBR0_NS
0xc4
TTBR1_NS
0xc5
CONTEXTIDR_NS
0xc6
PAR_NS
0xc7
AMAIR0_S
0xc8
AMAIR1_S
0xc9
AMAIR0_NS
0xca
AMAIR1_NS
0xcb
HMAIR0
0xcc
HMAIR1
0xcd
HAMAIR0
0xce
HAMAIR1
0xcf
HTCR
0xd0
VTCR
0xd1
TCR_EL3
0xd2
TCR_EL2
0xd3
VTCR_EL2
0xd4
DACR32_EL2
0xd5
CTICONTROL
0xd6
CTIINTACK
0xd7
CTIAPPSET
0xd8
CTICHANPULSE
0xd9
CTITRIGINSTATUS
0xda
CTITRIGOUTSTATUS
0xdb
CTICHINSTATUS
0xdc
CTICHOUTSTATUS
0xdd
CTIGATE
0xde
CTIITCTRL
0xdf
CTILAR
0xe0
UnknownCTI
0xe1
CTIINEN0
0xe2
CTIINEN1
0xe3
CTIINEN2
0xe4
CTIINEN3
0xe5
CTIINEN4
0xe6
CTIINEN5
0xe7
CTIINEN6
0xe8
CTIINEN7
0xe9
CTIOUTEN0
0xea
CTIOUTEN1
0xeb
CTIOUTEN2
0xec
CTIOUTEN3
0xed
CTIOUTEN4
0xee
CTIOUTEN5
0xef
CTIOUTEN6
0xf0
CTIOUTEN7
0xf1
CCSELR_EL1
0xf2
VPIDR_EL2
0xf3
SCTLR_EL1
0xf4
SCTLR_EL2
0xf5
SCTLR_EL3
0xf6
ACTLR_EL1
0xf7
ACTLR_EL2
0xf8
ACTLR_EL3
0xf9
CPACR_EL1
0xfa
CPTR_EL2
0xfb
CPTR_EL3
0xfc
SCR_EL3
0xfd
MDCR_EL2
0xfe
MDCR_EL3
0xff
HSTR_EL2
0x100
HACR_EL2
0x101
AFSR0_EL1
0x102
AFSR1_EL1
0x103
AFSR0_EL2
0x104
AFSR1_EL2
0x105
AFSR0_EL3
0x106
AFSR1_EL3
0x107
ESR_EL1
0x108
ESR_EL2
0x109
ESR_EL3
0x10a
CONTEXTIDR_EL1
0x10b
TEECR32_EL1
0x10c
DACR32_EL2
0x10d
IFSR32_EL2
0x10e
TEEHBR32_EL1
0x10f
SDER32_EL3
0x110
SPSR_EL1
0x111
SPSR_EL2
0x112
SPSR_EL3
0x113
FPSR
0x114
FPCR
0x115
DSPSR_EL0
0x116
DSPSR
0x117
DLR
0x118
DISR_EL1
0x119
VDISR_EL2
0x11a
VSESR_EL2
0x11b
ERRSELR_EL1
0x11c
ERXSTATUS_EL1
VALUE unsigned int
Value written to the register.
UNKNOWN unsigned int
Bits of the register which became unknown.

SYSREG_UPDATE64

Triggers when the system updates a register. Fields:

REG enum
Register number.
0x0
PMPCSR
0x1
TTBR0_64_S
0x2
TTBR1_64_S
0x3
PAR_64_S
0x4
TTBR0_64_NS
0x5
TTBR1_64_NS
0x6
PAR_64_NS
0x7
HTTBR
0x8
VTTBR
0x9
TTBR0_EL3
0xa
MAIR_EL3
0xb
AMAIR_EL3
0xc
TTBR0_EL2
0xd
MAIR_EL2
0xe
AMAIR_EL2
0xf
VTTBR_EL2
0x10
TCR_EL1
0x11
TTBR0_EL1
0x12
TTBR1_EL1
0x13
MAIR_EL1
0x14
AMAIR_EL1
0x15
PAR_EL1
0x16
CONTEXTIDR_EL1
0x17
VMPIDR_EL2
0x18
HCR_EL2
0x19
FAR_EL1
0x1a
FAR_EL2
0x1b
FAR_EL3
0x1c
HPFAR_EL2
0x1d
MAIR_EL1
0x1e
MAIR_EL2
0x1f
MAIR_EL3
0x20
VBAR_EL1
0x21
VBAR_EL2
0x22
VBAR_EL3
0x23
TPIDR_EL0
0x24
TPIDRRO_EL0
0x25
TPIDR_EL1
0x26
TPIDR_EL2
0x27
TPIDR_EL3
0x28
ELR_EL1
0x29
ELR_EL2
0x2a
ELR_EL3
0x2b
DLR_EL0
0x2c
MPIDR_EL1
0x2d
ERXFR_EL1
0x2e
ERXCTLR_EL1
0x2f
ERXADDR_EL1
0x30
ERXMISC0_EL1
0x31
ERXMISC1_EL1
VALUE unsigned int
Value written to the register.
UNKNOWN unsigned int
Bits of the register which became unknown.

SYSREG_WRITE64

System Coprocessor register write. Fields:

REGNUM enum
Internal register number.
0x4071
IC IALLUIS
0x4075
IC IALLU
0x4078
AT S1E1R
0x4083
TLBI VMALLE1IS
0x4087
TLBI VMALLE1
0x40b0-0x40bf 0x40f0-0x40f3
IMP DEF
0x40f4
RAMIDX
0x40f5-0x40ff
IMP DEF
0x4176
DC IVAC
0x4178
AT S1E1W
0x4183
TLBI VAE1IS
0x4187
TLBI VAE1
0x41b0-0x41bf 0x41f0-0x41ff
IMP DEF
0x4276
DC ISW
0x4278
AT S1E0R
0x427a
DC CSW
0x427e
DC CISW
0x4283
TLBI ASIDE1IS
0x4287
TLBI ASIDE1
0x42b0-0x42bf 0x42f0-0x42ff
IMP DEF
0x4378
AT S1E0W
0x4383
TLBI VAAE1IS
0x4387
TLBI VAAE1
0x43b0-0x43bf 0x43f0-0x43ff 0x44b0-0x44bf 0x44f0-0x44ff
IMP DEF
0x4583
TLBI VALE1IS
0x4587
TLBI VALE1
0x45b0-0x45bf 0x45f0-0x45ff 0x46b0-0x46bf 0x46f0-0x46ff
IMP DEF
0x4783
TLBI VAALE1IS
0x4787
TLBI VAALE1
0x47b0-0x47bf 0x47f0-0x47ff 0x48b0-0x48bf 0x48f0-0x48ff 0x49b0-0x49bf 0x49f0-0x49ff 0x4ab0-0x4abf 0x4af0-0x4aff 0x4bb0-0x4bbf 0x4bf0-0x4bff 0x4cb0-0x4cbf 0x4cf0-0x4cff 0x4db0-0x4dbf 0x4df0-0x4dff 0x4eb0-0x4ebf 0x4ef0-0x4eff 0x4fb0-0x4fbf 0x4ff0-0x4fff 0x50b0-0x50bf 0x50f0-0x50ff 0x51b0-0x51bf 0x51f0-0x51ff 0x52b0-0x52bf 0x52f0-0x52ff 0x53b0-0x53bf 0x53f0-0x53ff 0x54b0-0x54bf 0x54f0-0x54ff 0x55b0-0x55bf 0x55f0-0x55ff 0x56b0-0x56bf 0x56f0-0x56ff 0x57b0-0x57bf 0x57f0-0x57ff 0x58b0-0x58bf 0x58f0-0x58ff
IMP DEF
0x5974
DC ZVA
0x5975
IC IVAU
0x597a
DC CVAC
0x597b
DC CVAU
0x597e
DC CIVAC
0x59b0-0x59bf 0x59f0-0x59ff 0x5ab0-0x5abf 0x5af0-0x5aff 0x5bb0-0x5bbf 0x5bf0-0x5bff 0x5cb0-0x5cbf 0x5cf0-0x5cff 0x5db0-0x5dbf 0x5df0-0x5dff 0x5eb0-0x5ebf 0x5ef0-0x5eff 0x5fb0-0x5fbf 0x5ff0-0x5fff
IMP DEF
0x6078
AT S1E2R
0x6083
TLBI ALLE2IS
0x6087
TLBI ALLE2
0x60b0-0x60bf 0x60f0-0x60ff
IMP DEF
0x6178
AT S1E2W
0x6180
TLBI IPAS2E1IS
0x6183
TLBI VAE2IS
0x6184
TLBI IPAS2E1
0x6187
TLBI VAE2
0x61b0-0x61bf 0x61f0-0x61ff 0x62b0-0x62bf 0x62f0-0x62ff 0x63b0-0x63bf 0x63f0-0x63ff
IMP DEF
0x6478
AT S12E1R
0x6483
TLBI ALLE1IS
0x6487
TLBI ALLE1
0x64b0-0x64bf 0x64f0-0x64ff
IMP DEF
0x6578
AT S12E1W
0x6580
TLBI IPAS2LE1IS
0x6583
TLBI VALE2IS
0x6584
TLBI IPAS2LE1
0x6587
TLBI VALE2
0x65b0-0x65bf 0x65f0-0x65ff
IMP DEF
0x6678
AT S12E0R
0x6683
TLBI VMALLS12E1IS
0x6687
TLBI VMALLS12E1
0x66b0-0x66bf 0x66f0-0x66ff
IMP DEF
0x6778
AT S12E0W
0x67b0-0x67bf 0x67f0-0x67ff 0x68b0-0x68bf 0x68f0-0x68ff 0x69b0-0x69bf 0x69f0-0x69ff 0x6ab0-0x6abf 0x6af0-0x6aff 0x6bb0-0x6bbf 0x6bf0-0x6bff 0x6cb0-0x6cbf 0x6cf0-0x6cff 0x6db0-0x6dbf 0x6df0-0x6dff 0x6eb0-0x6ebf 0x6ef0-0x6eff 0x6fb0-0x6fbf 0x6ff0-0x6fff
IMP DEF
0x7078
AT S1E3R
0x7083
TLBI ALLE3IS
0x7087
TLBI ALLE3
0x70b0-0x70bf 0x70f0-0x70ff
IMP DEF
0x7178
AT S1E3W
0x7183
TLBI VAE3IS
0x7187
TLBI VAE3
0x71b0-0x71bf 0x71f0-0x71ff 0x72b0-0x72bf 0x72f0-0x72ff 0x73b0-0x73bf 0x73f0-0x73ff 0x74b0-0x74bf 0x74f0-0x74ff
IMP DEF
0x7583
TLBI VALE3IS
0x7587
TLBI VALE3
0x75b0-0x75bf 0x75f0-0x75ff 0x76b0-0x76bf 0x76f0-0x76ff 0x77b0-0x77bf 0x77f0-0x77ff 0x78b0-0x78bf 0x78f0-0x78ff 0x79b0-0x79bf 0x79f0-0x79ff 0x7ab0-0x7abf 0x7af0-0x7aff 0x7bb0-0x7bbf 0x7bf0-0x7bff 0x7cb0-0x7cbf 0x7cf0-0x7cff 0x7db0-0x7dbf 0x7df0-0x7dff 0x7eb0-0x7ebf 0x7ef0-0x7eff 0x7fb0-0x7fbf 0x7ff0-0x7fff
IMP DEF
0x8002
MDCCINT_EL1
0x8010
MDRAR_EL1
0x8200
OSDTRRX_EL1
0x8202
MDSCR_EL1
0x8203
OSDTRTX_EL1
0x8206
OSECCR_EL1
0x8400
DBGBVR0_EL1
0x8401
DBGBVR1_EL1
0x8402
DBGBVR2_EL1
0x8403
DBGBVR3_EL1
0x8404
DBGBVR4_EL1
0x8405
DBGBVR5_EL1
0x8410
OSLAR_EL1
0x8411
OSLSR_EL1
0x8413
OSDLR_EL1
0x8414
DBGPRCR_EL1
0x8500
DBGBCR0_EL1
0x8501
DBGBCR1_EL1
0x8502
DBGBCR2_EL1
0x8503
DBGBCR3_EL1
0x8504
DBGBCR4_EL1
0x8505
DBGBCR5_EL1
0x8600
DBGWVR0_EL1
0x8601
DBGWVR1_EL1
0x8602
DBGWVR2_EL1
0x8603
DBGWVR3_EL1
0x8678
DBGCLAIMSET_EL1
0x8679
DBGCLAIMCLR_EL1
0x867e
DBGAUTHSTATUS_EL1
0x8700
DBGWCR0_EL1
0x8701
DBGWCR1_EL1
0x8702
DBGWCR2_EL1
0x8703
DBGWCR3_EL1
0x9801
MDCCSR_EL0
0x9804
DBGDTR_EL0
0x9805
DBGDTRxX_EL0
0xa007
DBGVCR32_EL2
0xc000
MIDR_EL1
0xc001
ID_PFR0_EL1
0xc002
ID_ISAR0_EL1
0xc003
MVFR0_EL1
0xc004
ID_AA64PFR0_EL1
0xc005
ID_AA64DFR0_EL1
0xc006
ID_AA64ISAR0_EL1
0xc007
ID_AA64MMFR0_EL1
0xc010
SCTLR_EL1
0xc020
TTBR0_EL1
0xc040
SPSR_EL1
0xc041
SP_EL0
0xc042
SPSel
0xc051
AFSR0_EL1
0xc052
ESR_EL1
0xc060
FAR_EL1
0xc074
PAR_EL1
0xc0a2
MAIR_EL1
0xc0a3
AMAIR_EL1
0xc0b0-0xc0bf
IMP DEF
0xc0c0
VBAR_EL1
0xc0c1
ISR_EL1
0xc0e1
CNTKCTL_EL1
0xc0f0-0xc0f1
IL1D0
0xc0f2-0xc0ff
IMP DEF
0xc101
ID_PFR1_EL1
0xc102
ID_ISAR1_EL1
0xc103
MVFR1_EL1
0xc104
ID_AA64PFR1_EL1
0xc105
ID_AA64DFR1_EL1
0xc106
ID_AA64ISAR1_EL1
0xc107
ID_AA64MMFR1_EL1
0xc110
ACTLR_EL1
0xc120
TTBR1_EL1
0xc140
ELR_EL1
0xc151
AFSR1_EL1
0xc19e
PMINTENSET_EL1
0xc1b0-0xc1bf
IMP DEF
0xc1d0
CONTEXTIDR_EL1
0xc1f0
IL1D1
0xc1f1
DL1D1
0xc1f2-0xc1ff
IMP DEF
0xc201
ID_DFR0_EL1
0xc202
ID_ISAR2_EL1
0xc203
MVFR2_EL1
0xc204-0xc207
Reserved
0xc210
CPACR_EL1
0xc220
TCR_EL1
0xc242
CURREL
0xc29e
PMINTENCLR_EL1
0xc2b0-0xc2bf
IMP DEF
0xc2f0
IL1D2
0xc2f1
DL1D2
0xc2f2-0xc2ff
IMP DEF
0xc301
ID_AFR0_EL1
0xc302
ID_ISAR3_EL1
0xc303-0xc307
Reserved
0xc342
PAN
0xc3b0-0xc3bf
IMP DEF
0xc3f0
IL1D3
0xc3f1
DL1D3
0xc3f2-0xc3ff
IMP DEF
0xc401
ID_MMFR0_EL1
0xc402
ID_ISAR4_EL1
0xc403-0xc404
Reserved
0xc405
ID_AA64AFR0_EL1
0xc406-0xc407
Reserved
0xc4b0-0xc4bf
IMP DEF
0xc4d0
TPIDR_EL1
0xc4f0
IMP DEF
0xc4f1
DL1D4
0xc4f2-0xc4ff
IMP DEF
0xc500
MPIDR_EL1
0xc501
ID_MMFR1_EL1
0xc502
ID_ISAR5_EL1
0xc503-0xc504
Reserved
0xc505
ID_AA64AFR1_EL1
0xc506-0xc507
Reserved
0xc5b0-0xc5bf 0xc5f0-0xc5ff
IMP DEF
0xc600
REVIDR_EL1
0xc601
ID_MMFR2_EL1
0xc602-0xc607
Reserved
0xc6b0-0xc6bf 0xc6f0-0xc6ff
IMP DEF
0xc701
ID_MMFR3_EL1
0xc702-0xc707
Reserved
0xc7b0-0xc7bf 0xc7f0-0xc7ff
IMP DEF
0xc800
CCSIDR_EL1
0xc8b0-0xc8bf
IMP DEF
0xc8f0
L2ACTLR
0xc8f1
IMP DEF
0xc8f2
CPUACTLR_EL1
0xc8f3
CBAR_EL1
0xc8f4-0xc8ff
IMP DEF
0xc900
CLIDR_EL1
0xc9b0-0xc9bf 0xc9f0-0xc9f1
IMP DEF
0xc9f2
CPUECTLR_EL1
0xc9f3-0xc9ff
IMP DEF
0xcab0
L2CTLR
0xcab1-0xcabf 0xcaf0-0xcaf1
IMP DEF
0xcaf2
CPUMERRSR_EL1
0xcaf3-0xcaff
IMP DEF
0xcbb0
L2ECTLR
0xcbb1-0xcbbf 0xcbf0-0xcbf1
IMP DEF
0xcbf2
L2MERRSR_EL1
0xcbf3-0xcbff 0xccb0-0xccbf 0xccf0-0xccff 0xcdb0-0xcdbf 0xcdf0-0xcdff 0xceb0-0xcebf 0xcef0-0xceff
IMP DEF
0xcf00
AIDR_EL1
0xcfb0-0xcfbf 0xcff0-0xcfff
IMP DEF
0xd000
CSSELR_EL1
0xd0b0-0xd0bf 0xd0f0-0xd0ff 0xd1b0-0xd1bf 0xd1f0-0xd1ff 0xd2b0-0xd2bf 0xd2f0-0xd2ff 0xd3b0-0xd3bf 0xd3f0-0xd3ff 0xd4b0-0xd4bf 0xd4f0-0xd4ff 0xd5b0-0xd5bf 0xd5f0-0xd5ff 0xd6b0-0xd6bf 0xd6f0-0xd6ff 0xd7b0-0xd7bf 0xd7f0-0xd7ff
IMP DEF
0xd842
NZCV
0xd844
FPCR
0xd845
DSPSR_EL0
0xd89c
PMCR_EL0
0xd89d
PMCCNTR_EL0
0xd89e
PMUSERENR_EL0
0xd8b0-0xd8bf
IMP DEF
0xd8e0
CNTFRQ_EL0
0xd8e2
CNTP_TVAL_EL0
0xd8e3
CNTV_TVAL_EL0
0xd8e8
PMEVCNTR0_EL0
0xd8ec
PMEVTYPER0_EL0
0xd8f0-0xd8ff
IMP DEF
0xd900
CTR_EL0
0xd942
DAIF
0xd944
FPSR
0xd945
DLR_EL0
0xd99c
PMCNTENSET_EL0
0xd99d
PMXEVTYPER_EL0
0xd9b0-0xd9bf
IMP DEF
0xd9e0
CNTPCT_EL0
0xd9e2
CNTP_CTL_EL0
0xd9e3
CNTV_CTL_EL0
0xd9e8
PMEVCNTR1_EL0
0xd9ec
PMEVTYPER1_EL0
0xd9f0-0xd9ff
IMP DEF
0xda9c
PMCNTENCLR_EL0
0xda9d
PMXEVCNTR_EL0
0xdab0-0xdabf
IMP DEF
0xdad0
TPIDR_EL0
0xdae0
CNTVCT_EL0
0xdae2
CNTP_CVAL_EL0
0xdae3
CNTV_CVAL_EL0
0xdae8
PMEVCNTR2_EL0
0xdaec
PMEVTYPER2_EL0
0xdaf0-0xdaff
IMP DEF
0xdb9c
PMOVSCLR_EL0
0xdb9e
PMOVSSET_EL0
0xdbb0-0xdbbf
IMP DEF
0xdbd0
TPIDRRO_EL0
0xdbe8
PMEVCNTR3_EL0
0xdbec
PMEVTYPER3_EL0
0xdbf0-0xdbff
IMP DEF
0xdc9c
PMSWINC_EL0
0xdcb0-0xdcbf
IMP DEF
0xdce8
PMEVCNTR4_EL0
0xdcec
PMEVTYPER4_EL0
0xdcf0-0xdcff
IMP DEF
0xdd9c
PMSELR_EL0
0xddb0-0xddbf
IMP DEF
0xdde8
PMEVCNTR5_EL0
0xddec
PMEVTYPER5_EL0
0xddf0-0xddff
IMP DEF
0xde9c
PMCEID0_EL0
0xdeb0-0xdebf 0xdef0-0xdeff
IMP DEF
0xdf00
DCZID_EL0
0xdf9c
PMCEID1_EL0
0xdfb0-0xdfbf
IMP DEF
0xdfef
PMCCFILTR_EL0
0xdff0-0xdfff
IMP DEF
0xe000
VPIDR_EL2
0xe010
SCTLR_EL2
0xe011
HCR_EL2
0xe020
TTBR0_EL2
0xe021
VTTBR_EL2
0xe030
DACR32_EL2
0xe040
SPSR_EL2
0xe041
SP_EL1
0xe043
SPSR_IRQ
0xe051
AFSR0_EL2
0xe052
ESR_EL2
0xe053
FPEXC32_EL2
0xe060
FAR_EL2
0xe0a2
MAIR_EL2
0xe0a3
AMAIR_EL2
0xe0b0-0xe0bf
IMP DEF
0xe0c0
VBAR_EL2
0xe0e1
CNTHCTL_EL2
0xe0e2
CNTHP_TVAL_EL2
0xe0f0-0xe0ff
IMP DEF
0xe110
ACTLR_EL2
0xe111
MDCR_EL2
0xe140
ELR_EL2
0xe143
SPSR_ABT
0xe150
IFSR32_EL2
0xe151
AFSR1_EL2
0xe1b0-0xe1bf
IMP DEF
0xe1e2
CNTHP_CTL_EL2
0xe1f0-0xe1ff
IMP DEF
0xe211
CPTR_EL2
0xe220
TCR_EL2
0xe221
VTCR_EL2
0xe243
SPSR_UND
0xe2b0-0xe2bf
IMP DEF
0xe2d0
TPIDR_EL2
0xe2e2
CNTHP_CVAL_EL2
0xe2f0-0xe2ff
IMP DEF
0xe311
HSTR_EL2
0xe343
SPSR_FIQ
0xe3b0-0xe3bf
IMP DEF
0xe3e0
CNTVOFF_EL2
0xe3f0-0xe3ff
IMP DEF
0xe460
HPFAR_EL2
0xe4b0-0xe4bf 0xe4f0-0xe4ff
IMP DEF
0xe500
VMPIDR_EL2
0xe5b0-0xe5bf 0xe5f0-0xe5ff 0xe6b0-0xe6bf 0xe6f0-0xe6ff
IMP DEF
0xe711
HACR_EL2
0xe7b0-0xe7bf 0xe7f0-0xe7ff 0xe8b0-0xe8bf 0xe8f0-0xe8ff 0xe9b0-0xe9bf 0xe9f0-0xe9ff 0xeab0-0xeabf 0xeaf0-0xeaff 0xebb0-0xebbf 0xebf0-0xebff 0xecb0-0xecbf 0xecf0-0xecff 0xedb0-0xedbf 0xedf0-0xedff 0xeeb0-0xeebf 0xeef0-0xeeff 0xefb0-0xefbf 0xeff0-0xefff
IMP DEF
0xf010
SCTLR_EL3
0xf011
SCR_EL3
0xf020
TTBR0_EL3
0xf040
SPSR_EL3
0xf041
SP_EL2
0xf051
AFSR0_EL3
0xf052
ESR_EL3
0xf060
FAR_EL3
0xf0a2
MAIR_EL3
0xf0a3
AMAIR_EL3
0xf0b0-0xf0bf
IMP DEF
0xf0c0
VBAR_EL3
0xf0f0-0xf0ff
IMP DEF
0xf110
ACTLR_EL3
0xf111
SDER32_EL3
0xf113
MDCR_EL3
0xf140
ELR_EL3
0xf151
AFSR1_EL3
0xf1b0-0xf1bf
IMP DEF
0xf1c0
RVBAR_EL3
0xf1f0-0xf1ff
IMP DEF
0xf211
CPTR_EL3
0xf220
TCR_EL3
0xf2b0-0xf2bf
IMP DEF
0xf2c0
RMR_EL3
0xf2d0
TPIDR_EL3
0xf2f0-0xf2ff 0xf3b0-0xf3bf 0xf3f0-0xf3ff 0xf4b0-0xf4bf 0xf4f0-0xf4ff 0xf5b0-0xf5bf 0xf5f0-0xf5ff 0xf6b0-0xf6bf 0xf6f0-0xf6ff 0xf7b0-0xf7bf 0xf7f0-0xf7ff 0xf8b0-0xf8bf
IMP DEF
0xf8e2
CNTPS_TVAL_EL1
0xf8f0-0xf8ff 0xf9b0-0xf9bf
IMP DEF
0xf9e2
CNTPS_CTL_EL1
0xf9f0-0xf9ff 0xfab0-0xfabf
IMP DEF
0xfae2
CNTPS_CVAL_EL1
0xfaf0-0xfaff 0xfbb0-0xfbbf 0xfbf0-0xfbff 0xfcb0-0xfcbf 0xfcf0-0xfcff 0xfdb0-0xfdbf 0xfdf0-0xfdff 0xfeb0-0xfebf 0xfef0-0xfeff 0xffb0-0xffbf 0xfff0-0xffff
IMP DEF
VALUE unsigned int
The new value written.
UPDATED_VALUE unsigned int
Updated value of the register now it has been written.
UNDEF bool
The register accessed is undefined.
CORE_NUM unsigned int
Core number in a multi processor.

UNALIGNED_LDST_RETIRED

Processor unaligned load/store. Fields:

VADDR unsigned int
The virtual address of the access.
RESPONSE enum
0=Aborted, 1=OK, 2=Exclusive Failed.
0x0
Aborted
0x1
OK
0x2
Failed
LOCK enum
Normal, exclusive or locked access.
0x0
Normal
0x1
Exclusive
0x2
Locked
TRANS bool
Is this a translated access.
ACQREL enum
Is this an acquire/release.
0x0
None
0x1
Global
0x2
Local
SIZE unsigned int
Width of the access in bytes. Only required if DATA is not traced.
ELEMENT_SIZE unsigned int
Width of each element.
PADDR unsigned int
The physical (translated) address.
NSDESC unsigned int
The physical address non-secure bit.
PADDR2 unsigned int
If different from PADDR, the physical address of the second page of the access.
NSDESC2 unsigned int
The second page physical address non-secure bit.
DATA unsigned int
The data read or written.

VFP_D_REGS

VFP/NEON D 64 bit register write. Fields:

ID unsigned int
The register number.
VALUE unsigned int
The new value written to the register.
OLD_VALUE unsigned int
The old value overwritten.
CORE_NUM unsigned int
Core number in a multi processor.
ALIASING enum
Type of register aliasing used.
0x1
AArch32
0x2
AArch64
MASK unsigned int
Mask for partial register update.

VFP_Q_REGS

VFP/NEON Q 128 bit register write. Fields:

ID unsigned int
The register number.
VALUE unsigned int
The new value written to the register.
OLD_VALUE unsigned int
The old value overwritten.
CORE_NUM unsigned int
Core number in a multi processor.
ALIASING enum
Type of register aliasing used.
0x1
AArch32
0x2
AArch64
MASK unsigned int
Mask for partial register update.

VFP_SYS_REGS

Writes to the VFP/NEON units system registers. Fields:

ID enum
Which VFP system register is written.
0x1
FPSCR
0x8
FPEXC
VALUE unsigned int
The new value written to the VFP system register.
OLD_VALUE unsigned int
The register's old value overwritten.
CORE_NUM unsigned int
Core number in a multi processor.

VFP_S_REGS

VFP/NEON S 32 bit register write. Fields:

ID unsigned int
The register number.
VALUE unsigned int
The new value written to the register.
OLD_VALUE unsigned int
The old value overwritten.
CORE_NUM unsigned int
Core number in a multi processor.
ALIASING enum
Type of register aliasing used.
0x1
AArch32
0x2
AArch64

WFE_END

WFE ended. Fields:

INST_COUNT unsigned int
Ticks count when leaving WFE.

WFE_EVENT_REGISTER

WFE event register status: set/clear, reason. Fields:

INST_COUNT unsigned int
Ticks count.
REASON enum
Reason for set/clear. Only REASON==0 (Cleared by WFE) clears the bit, all other reasons set it.
0x0
Cleared by WFE
0x1
Set by SEV instruction (this or another core)
0x2
Set by Exception Return
0x3
Set by external FIQ
0x4
Set by external IRQ
0x5
Set by external Abort
0x6
Set by virtual FIQ
0x7
Set by virtual IRQ
0x8
Set by virtual Abort
0x10
Set by debug request
0x11
Set by debug halt
0x12
Set by debug OS unlock
0x20
Set by pending exception (M class only)
0x21
Set by exception taken (M class only)
0x40
Set by SEVL instruction
0x80
Set by Global Timer event
0x100
Set by Global Virtual Timer event
0x200
Set by loss of monitor reservation

WFE_IGNORED

WFE ignored. Fields:

INST_COUNT unsigned int
Ticks count when ignoring WFE.
TRAPPED bool
This WFE was trapped.
EVENT bool
This WFE was ignored because the event register was set.

WFE_START

WFE entered. Fields:

INST_COUNT unsigned int
Ticks count when entering WFE.

WFI_END

WFI ended. Fields:

INST_COUNT unsigned int
Ticks count when leaving WFI.

WFI_IGNORED

WFI ignored. Fields:

INST_COUNT unsigned int
Ticks count when ignoring WFI.
TRAPPED bool
This WFI was trapped.
DISABLED bool
This WFI was ignored because WFI is disabled.

WFI_START

WFI entered. Fields:

INST_COUNT unsigned int
Ticks count when entering WFI.

WFI_WAKEUP

WFI wakeup. Fields:

INST_COUNT unsigned int
Ticks count when WFI wakeup occurred.
REASON enum
Reason for wakeup.
0x0
Reset signal
0x1
FIQ signal
0x2
IRQ signal
0x3
Abort signal
0x4
VFIQ signal
0x5
VIRQ signal
0x6
VAbort signal
0x7
Debug request signal
0x8
Debug halt signal
0x9
Debug OS Unlock request
0xc
Pending exception
0xd
Global timer event stream
0xe
Global virtual timer event stream
0xf
loss of global monitor reservation
0x10
IMP DEF wakeup mechanism (CADI register write)

ARMCortexA57xnCT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of Linux on an example system.

ARMCortexA57xnCT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • The value of the AArch64 PMCEID0_EL0 register, and the AArch32 alias of this register, differs in the model from the TRM value. The model value reflects the model counters.
  • The mechanisms for setting the affinity fields of the MPIDR. The RTL has two ports:
    • CLUSTERIDAFF1[7:0].
    • CLUSTERIDAFF2[7:0].
    AFF1 sets the value of MPIDR bits[15:8] and AFF2 sets the value of MPIDR bits[23:16]. In contrast, the model has a single CLUSTER_ID port. This difference allows the setting of bits[23:8] of the MPIDR using bits[15:0] of the CLUSTER_ID value.
  • The memory mapped debug registers have a view for cores and a view for external debug agents. In the model, these views require two PVBus ports. In hardware, the system designer decides how the implementation differentiates the views.
  • In the model, a single peer event port combines the functionality of the eventi and evento signals in the RTL.
  • The Generic Timers are Programmer’s View (PV) level abstractions: a model-specific protocol connects the cntvalueb port to the MemoryMappedCounterModule.
  • The GIC CPU Interface is a PV level abstraction: a model-specific protocol connects the GIC CPU Interface to the GIC Distributor.
  • The CoreSight Cross Trigger Interface (CTI) is a PV level abstraction: the interface is a model-specific one.
  • The model has no mechanism to read the internal memory that the Cache and TLB structures use, through the implementation defined region of the system coprocessor interface. This memory includes the RAM Index Register, IL1DATA Registers, DL1DATA Registers, and associated functionality.
  • The model does not implement:
    • ETM registers.
    • The PMUEVENT bus.
    • The WARMRESETREQ signal. However, the warm reset code sequence (see the section Code sequence to request a Warm reset as a result of RMR_ELx.RR in the ARMv8-A Architecture Reference Manual) makes the model simulate a warm reset of the core.
    • The PMUSNAPSHOTREQ and PMUSNAPSHOTACK signals.
    • The EXTERRIRQ and INTERRIRQ signals.
    • Processor dynamic-retention signals.
    • The SYSBARDISABLE signal.
    • The DBGPWRDUP, DBGPWRUPREQ, DBGNOPWRDWN, and DBGRSTREQ debug power management signals.
a ARMv8 Cryptography Extensions require a separate package, which is subject to export license conditions. Contact ARM for details.
b The system designer decides whether a debug APB ties the external debug view with other system views. In the model, use a PVBusDecoder to direct traffic to the correct port.
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