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ARMCortexA5MPxnCT component

This section describes the ARMCortexA5MPxnCT component.

ARMCortexA5MPxnCT - about

This C++ component is a model of r0p0 of a Cortex-A5 processor. The n shows the number of cores.

This component implements peripherals that are not present in the basic Cortex-A5 processor:

  • Snoop Control Unit (SCU).
  • Generic Interrupt Controller (GIC).
  • Private timer and watchdog for each processor.
  • Global timer.
  • Advanced Coherency Port (ACP).

ARMCortexA5MPxnCT - ports

This section describes the ports.

Table 3-50 ARMCortexA5MPxnCT ports

Name Protocol Type Description
acp_s PVBus Slave Slave channel.
cfgend[0-3] Signal Slave Initialize to BE8 endianness after a reset.
cfgnmfi[0-3] Signal Slave Enable nonmaskable FIQ interrupts after a reset.
cfgsdisable Signal Slave Disable write access to some GIC registers.
clk_in ClockSignal Slave Main processor clock input.
clusterid Value Slave Value read in MPIDR register.
cp15sdisable[0-3] Signal Slave Disable write access to some cp15 registers.
event Signal Peer Event input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
filteren Signal Slave Enable filtering of address ranges between master bus ports.
filterend Value Slave End of region mapped to pvbus_m1.
filterstart Value Slave Start of region mapped to pvbus_m1.
fiq[0-3] Signal Slave Processor FIQ signal input.
irq[0-3] Signal Slave Processor IRQ signal input.
ints[0-223] Signal Slave Shared peripheral interrupts.
periphbase Value Slave Base of private peripheral region.
periphclk_in ClockSignal Slave Timer/watchdog clock rate.
periphreset Signal Slave Timer and GIC reset signal.
pmuirq[0-3] Signal Master Performance Monitoring Unit (PMU) interrupt signal.
pvbus_m0 PVBus Master AXI master 0 bus master channel.
pvbus_m1 PVBus Master AXI master 1 bus master channel.
pwrctli[0-3] Value Slave Reset value for SCU processor status register.
pwrctlo[0-3] Value Master SCU processor status register bits.
reset[0-3] Signal Slave Individual processor reset signal.
scureset Signal Slave SCU reset signal.
smpnamp[0-3] Signal Master Indicates which processors are in SMP mode.
standbywfe[0-3] Signal Master Indicates if a processor is in WFE state.
standbywfi[0-3] Signal Master Indicates if a processor is in WFI state.
teinit[0-3] Signal Slave Initialize to take exceptions in T32 state after a reset.
ticks[0-3] InstructionCount Master Processor instruction count for visualization.
vinithi[0-3] Signal Slave Initialize with high vectors enabled after a reset.
wdreset[0-3] Signal Slave Watchdog timer reset signal.
wdresetreq[0-3] Signal Master Watchdog timer IRQ outputs.

ARMCortexA5MPxnCT - parameters

The parameters are set once, irrespective of the number of cores. Each core has its own parameters.

Table 3-51 ARMCortexA5MPxnCT cluster parameters

Name Type Allowed values Default value Description
CLUSTER_ID int 0-15 0 Cluster ID value.
CFGSDISABLE bool true, false false Disable some accesses to GIC registers.
dcache-state_modelled bool true, false false Set whether or not D-cache has stateful implementation.
device-accurate-tlb bool true, false falsea Specify whether or not all TLBs are modeled.
dic-spi_count int 0-223, in increments of 32 64 Number of shared peripheral interrupts implemented.
FILTEREN bool true, false false Enable filtering of accesses through pvbus_m0.
FILTERSTART int Align on 1MB boundary. 0x0 Base of region filtered to pvbus_m0.
FILTEREND int Align on 1MB boundary. 0x0 End of region filtered to pvbus_m0.
icache-state_modelled bool true, false false Set whether or not I-cache has stateful implementation.
PERIPHBASE int - 0x13080000b Base address of peripheral memory space.

Table 3-52 ARMCortexA5MPxnCT core parameters

Name Type Allowed values Default value Description
ase-presentc bool true, false true Set whether or not the model has NEON™ support.
CFGEND bool true, false false Initialize to BE8 endianness.
CFGNMFI bool true, false false Enable nonmaskable FIQ interrupts on startup.
CP15SDISABLE bool true, false false Initialize to disable access to some CP15 registers.
cpi_div int 1-0x7FFFFFFF 1 Divider for calculating Cycles Per Instruction (CPI).
cpi_mul int 1-0x7FFFFFFF 1 Multiplier for calculating CPI.
dcache-size int 4KB, 8KB, 16KB, 32KB, 64KB 0x8000 Set D-cache size in bytes.
icache-size int 4KB, 8KB, 16KB, 32KB, 64KB 0x8000 Set I-cache size in bytes.
min_sync_level int 0-3 0 Controls the minimum syncLevel.
POWERCTLI int 0-3 0 Default power control state for core.
SMPnAMP bool true, false false Set whether or not the core is part of a coherent domain. This parameter is a model only parameter, not a synthesize option or a configuration port. In hardware, it is a design choice.
semihosting-cmd_line string No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable bool true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-ARM_SVC int 0x000000-0xFFFFFF 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC int 0x00-0xFF 0xAB T32 SVC number for semihosting.
semihosting-heap_base int 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit int 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base int 0x00000000-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit int 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of stack limit.
TEINIT bool true, false false T32 exception enable. The default has exceptions including reset handled in A32 state.
vfp-enable_at_resetd bool true, false false Enable coprocessor access and VFP at reset.
vfp-presentc bool true, false true Set whether or not model has VFP support.
VINITHI bool true, false false Initialize with high vectors enabled.

ARMCortexA5MPxnCT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the coprocessor 14 registers and the integration and test registers.

ARMCortexA5MPxnCT - caches

This component implements L1 cache as architecturally defined, but does not implement L2 cache. If you require an L2 cache you can add a PL310 Level 2 Cache Controller component.

Cache and TLB component visibility

If a core model has a cache model available, to create it and make it visible, enable it. To enable the cache model and be ready to use cache CADI, set these model parameters:

  • l1_icache-state_modelled
  • l1_dcache-state_modelled

To use cache and TLB viewers, connect the cache and TLB CADI components.

ARMCortexA5MPxnCT - debug features

This component exports a CADI debug interface.

ARMCortexA5MPxnCT - debug - registers

All core, VFP, and CP15 registers are visible in the debugger.

The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior.

This component also exports the SCU, Watchdog/Timer and GIC registers.

ARMCortexA5MPxnCT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexA5MPxnCT - debug - memory

This component presents two 4GB views of virtual memory, one as seen from secure mode and one as seen from normal mode.

ARMCortexA5MPxnCT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of Linux on an example system.

ARMCortexA5MPxnCT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • There is a single memory port combining instruction, data, DMA and peripheral access.
  • The GIC does not respect the CFGSDISABLE signal. This leads to some registers being accessible when they must not be.
  • The SCU enable bit is ignored. The SCU is always enabled.
  • The SCU ignores the invalidate all register.
  • The Broadcast TLB or cache operations in this model do not cause other cores in the cluster that are asleep because of Wait For Interrupt (WFI) to wake up.
  • The RR bit in the SCTLR is ignored.
  • The Power Control Register in the system control coprocessor is implemented but writing to it does not change the behavior of the model.
  • When modeling the SCU, coherency operations are represented by a memory write followed by a read to refill from memory, rather than using cache-to-cache transfers.
a Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.
b If you are using this component on a VE model platform, this parameter is set automatically to 0x1F000000 and is not visible in the parameter list.
c The ase-present and vfp-present parameters configure the synthesis options.
vfp present and ase present
NEON and VFPv3-D32 supported.
vfp present and ase not present
VFPv3-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.
vfp not present and ase not present
Model has neither NEON nor VFPv3-D32 support.
d This is a model specific behavior with no hardware equivalent.
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