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ARMCortexA72xnCT component

This section describes the ARMCortexA72xnCT component.

ARMCortexA72xnCT - about

This C++ component is a model of r0p0 of an ARMv8-A Cortex®-A72 processor containing from one to four cores. The n shows the number of cores.

ARMCortexA72xnCT - ports

This section describes the ports.

Table 3-9 ARMCortexA72xnCT ports

Name Protocol Type Description
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
clrexmonack Signal Master Acknowledge handshake signal for the clrexmonreq signal.
clrexmonreq Signal Slave Signals the clearing of an external global exclusive monitor.
pvbus_m0 PVBus Master The core will generate bus requests on this port.
acp_s PVBus Slave AXI ACP slave port.
virtio_s PVBus Slave The virtio coherent port, hooks directly into the L2 system and becomes coherent (assuming attributes are set correctly).
reset[4] Signal Slave Raising this signal will put the core into reset mode.
cpuporeset[4] Signal Slave Raising this signal will put the core into reset mode.
presetdbg Signal Slave Raising this signal will put the core into reset mode.
l2reset Signal Slave Raising this signal will put the core into reset mode.
l2flushreq Signal Slave Request flush of L2 memory system.
l2flushdone Signal Master Flush of L2 memory system complete.
romaddr Value_64 Slave Debug ROM base address.
romaddrv Signal Slave Debug ROM base address valid.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE.
standbywfe[4] Signal Master This signal indicates if a core is in WFE state.
standbywfi[4] Signal Master This signal indicates if a core is in WFI state.
standbywfil2 Signal Master This signal indicates if a core is in WFI state.
dbgnopwrdwn[4] Signal Master This signal relates to core power down.
dbgpwrupreq[4] Signal Master This signal relates to core power down.
cfgsdisable Signal Slave This signal disables write access to some secure Interrupt Controller registers.
smpen[4] Signal Master This signals AMP or SMP mode for each core.
irq[4] Signal Slave This signal drives the core's interrupt handling.
fiq[4] Signal Slave This signal drives the core's fast-interrupt handling.
virq[4] Signal Slave This signal is a virtualized version of the previous one.
vfiq[4] Signal Slave This signal is a virtualized version of the previous one.
sei[4] Signal Slave Per core System Error physical pins.
rei[4] Signal Slave Per core System Error physical pins.
vsei[4] Signal Slave Per core System Error physical pins.
pmuirq[4] Signal Master Interrupt signal from performance monitoring unit.
commirq[4] Signal Master Interrupt signal from debug communications channel.
commrx[4] Signal Master Receive portion of Data Transfer Register full.
commtx[4] Signal Master Transmit portion of Data Transfer Register empty.
vcpumntirq[4] Signal Master Interrupt signal for virtual CPU maintenance IRQ.
clusterid Value Slave The port reads the value in CPU ID register field, bits[11:8] of the MPIDR.
cp15sdisable[4] Signal Slave This signal disables write access to some system control processor registers.
cfgte[4] Signal Slave This signal provides default exception handling state.
ticks[4] InstructionCount Master This port should be connected to one of the two ticks ports on a 'visualization' component, in order to display a running instruction count.
vinithi[4] Signal Slave This signal controls of the location of the exception vectors at reset.
cfgend[4] Signal Slave This signal is for EE bit initialization.
periphbase Value_64 Slave This port sets the base address of private peripheral region.
rvbaraddr[4] Value_64 Slave Reset vector base address.
aa64naa32[4] Signal Slave Register width after reset.
cryptodisable[4] Signal Slave Disable cryptography extensions after reset.
cntvalueb CounterInterface Slave Interface to SoC level counter module.
dbgen[4] Signal Slave External debug interface.
spiden[4] Signal Slave External debug interface.
niden[4] Signal Slave External debug interface.
spniden[4] Signal Slave External debug interface.
dbgack[4] Signal Master External debug interface.
edbgrq[4] Signal Slave External debug interface.
dev_debug_s PVBus Slave External debug interface.
memorymapped_debug_s PVBus Slave External debug interface.
cti[4] v8EmbeddedCrossTrigger_controlprotocol Master Cross trigger matrix port.
ctidbgirq[4] Signal Master Cross trigger matrix port.
CNTPNSIRQ[4] Signal Master The per-EL counter signals master port.
CNTPSIRQ[4] Signal Master The per-EL counter signals master port.
CNTVIRQ[4] Signal Master The per-EL counter signals master port.
CNTHPIRQ[4] Signal Master The per-EL counter signals master port.
broadcastinner Signal Slave ACE defined pins.
broadcastouter Signal Slave ACE defined pins.
broadcastcachemaint Signal Slave ACE defined pins.
gicv3_redistributor_s[1] GICv3Comms Slave GICv3 AXI-stream port.

ARMCortexA72xnCT - parameters

This section describes the parameters.

ARMCortexA72xnCT cluster parameters

Table 3-10 ARMCortexA72xnCT cluster parameters

Name Type Allowed values Default value Description
CLUSTER_ID uint32_t 0x0-0xFFFF 0x0 -
dcache-state_modelled bool true, false false -
icache-state_modelled bool true, false false -
PERIPHBASE uint64_t 0x0-0xFFFFFFFFFFF 0x13080000 -
l2cache-size uint32_t 0x80000-0x200000 0x80000 L2 cache size in bytes.
GICDISABLE bool true, false true -

ARMCortexA72xnCT cache latency cluster parameters

Note

  • These latencies are only effective when you enable cache-state modeling.
  • Timing annotation for transactions downstream of the cache models propagates through the cache models.

Table 3-11 ARMCortexA72xnCT cache latency cluster parameters

Parameter Type Allowed values Default value Description
dcache-maintenance_latency uint64_t - 0x0 L1 D-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
dcache-read_latency uint64_t - 0x0 L1 D-cache timing annotation latency for read accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-snoop_data_transfer_latency uint64_t - 0x0 L1 D-cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-write_latency uint64_t - 0x0 L1 D-cache timing annotation latency for write accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
icache-maintenance_latency uint64_t - 0x0 L1 I-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when icache-state_modelled=true.
icache-read_latency uint64_t - 0x0 L1 I-cache timing annotation latency for read accesses given in ticks per byte accessed. For use when icache-state_modelled=true.
l2cache-maintenance_latency uint64_t - 0x0 L2 cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
l2cache-read_latency uint64_t - 0x0 L2 cache timing annotation latency for read accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_data_transfer_latency uint64_t - 0x0 L2 cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_issue_latency uint64_t - 0x0 L2 cache timing annotation latency for snoop accesses issued by this cache in total ticks. For use when dcache-state_modelled=true.
l2cache-write_latency uint64_t - 0x0 L2 cache timing annotation latency for write accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.

ARMCortexA72xnCT core parameters

Table 3-12 ARMCortexA72xnCT core parameters

Name Type Allowed values Default value Description
CFGEND bool true, false false -
CP15SDISABLE bool true, false false -
CFGTE bool true, false false -
VINITHI bool true, false false -
vfp-enable_at_reset bool true, false false -
semihosting-enable bool true, false true -
semihosting-ARM_SVC uint32_t 0x0-0xFFFFFF 0x123456 -
semihosting-Thumb_SVC uint32_t 0x0-0xFF 0xAB -
semihosting-cmd_line string - "" -
semihosting-heap_base uint32_t 0x0-0xFFFFFFFF 0x0 -
semihosting-heap_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 -
semihosting-stack_base uint32_t 0x0-0xFFFFFFFF 0x10000000 -
semihosting-stack_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 -
semihosting-cwd string - "" Base directory for semihosting file access.
RVBARADDR uint64_t 0x0-0xFFFFFFFFFFF 0x0 -
min_sync_level uint32_t 0x0-0x3 0x0 Runtime parameter. Force minimum syncLevel (0=off=default, 1=syncState, 2=postInsnIO, 3=postInsnAll).
cpi_mul uint32_t 0x1-0x7FFFFFFF 0x1 Runtime parameter. Multiplier for calculating CPI (Cycles Per Instruction).
cpi_div uint32_t 0x1-0x7FFFFFFF 0x1 Runtime parameter. Divider for calculating CPI (Cycles Per Instruction).
AA64nAA32 bool true, false true -
CRYPTODISABLE bool true, false false -
max_code_cache uint32_t 0x0-0xFFFFFFFFFFFFFFFF 67108864 Maximum number of bytes for caching code translations.
DBGROMADDRV bool true, false true -
DBGROMADDR uint64_t 0x0-0xffffFFFFffff 0x22000000 -

ARMCortexA72xnCT TLB latency cluster parameters

Note

Timing annotation for transactions downstream of the TLB model propagates through the TLB model.

Table 3-13 ARMCortexA72xnCT TLB latency cluster parameters

Parameter Type Allowed values Default value Description
ptw_latency uint32_t - 0x0 Page table walker latency for Timing Annotation (TA), in simulation ticks.
tlb_latency uint32_t - 0x0 TLB latency for TA, in simulation ticks.
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