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ARMCortexA73xnCT component

This section describes the ARMCortexA73xnCT component.

ARMCortexA73xnCT - about

This component is a model of r0p2 of an ARMv8-A Cortex®-A73 processor containing from one to four cores. The n shows the number of cores.

ARMCortexA73xnCT - ports

This section describes the ports.

Table 3-4 ARMCortexA73xnCT ports

Name Protocol Type Description
aa64naa32[4] Signal Slave Register width state after reset.
acp_s PVBus Slave Bus slave that the processor receives coherency transactions on. It is a Programmer’s View (PV) of the Advanced Extensible Interface (AXI) Accelerator Coherency Port (ACP) slave port.
broadcastcachemaint Signal Slave Enable broadcasting of cache maintenance operations to downstream caches.
broadcastinner Signal Slave Enable broadcasting of inner shareable transactions.
broadcastouter Signal Slave Enable broadcasting of outer shareable transactions.
cfgend[4] Signal Slave Configure endianness at reset.
cfgsdisable Signal Slave Disables write access to some secure Interrupt Controller registers.
cfgte[4] Signal Slave Initialize to take exceptions in T32 state after reset.
clk_in ClockSignal Slave Processor clock input, for determining the rate of instruction execution relative to other system components.
clrexmonack Signal Master Acknowledge handshake signal for the clrexmonreq signal.
clrexmonreq Signal Slave Signals the clearing of an external global exclusive monitor.
clusterid Value Slave Master ID, bits[23:8] of the MPIDR using bits[15:0] of the CLUSTER_ID value.
CNTHPIRQ[4] Signal Master Hypervisor physical timer interrupt.
CNTPNSIRQ[4] Signal Master Non-secure physical timer interrupt.
CNTPSIRQ[4] Signal Master Secure physical timer interrupt.
cntvalueb CounterInterface Slave Interface to SoC level counter module.
CNTVIRQ[4] Signal Master Virtual timer interrupt.
commirq[4] Signal Master Interrupt signal from debug communications channel.
commrx[4] Signal Master Receive portion of Data Transfer Register full.
commtx[4] Signal Master Transmit portion of Data Transfer Register empty.
cp15sdisable[4] Signal Slave This signal disables write access to some system control processor registers.
cpuporeset[4] Signal Slave Power on reset. Initializes all the processor logic, including debug logic.
cryptodisable[4] Signal Slave Disable cryptography extensions after reset.a
cti[4] v8EmbeddedCrossTrigger_controlprotocol Master Cross Trigger Matrix port.
ctidbgirq[4] Signal Master Cross Trigger Interface (CTI) interrupt trigger output.
dbgack[4] Signal Master Debug acknowledge.
dbgen[4] Signal Slave Invasive debug enable.
dbgnopwrdwn[4] Signal Master Emulate core power down.
dbgpwrupreq[4] Signal Master Core power up request.
dev_debug_s PVBus Slave Debug Advanced Peripheral Bus (APB) as exposed to external debug agents.b.
edbgrq[4] Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE.
fiq[4] Signal Slave Drives fast-interrupt handling by the core.
gicv3_redistributor_s[4] GICv3Comms Slave GICv3 AXI-stream port.
irq[4] Signal Slave Drives interrupt handling by the core.
l2flushdone Signal Master Flush of L2 memory system complete.
l2flushreq Signal Slave Request flush of L2 memory system.
l2reset Signal Slave Reset the shared L2 memory system controller.
memorymapped_debug_s PVBus Slave Debug APB as exposed to other system agents.b
niden[4] Signal Slave Non-invasive debug enable.
periphbase Value_64 Slave Sets the base address of the private peripheral region.
pmuirq[4] Signal Master Interrupt signal from performance monitoring unit.
presetdbg Signal Slave Initialize the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_m0 PVBus Master Bus master that the processor generates transactions on. This port is a PV representation of the AXI master port.
rei[4] Signal Slave Individual processor RAM Error Interrupt signal input.
reset[4] Signal Slave Individual processor reset.
romaddr Value_64 Slave Debug ROM base address.
romaddrv Signal Slave Debug ROM base address valid.
rvbaraddr[4] Value_64 Slave Reset vector base address.
sei[4] Signal Slave Individual processor System Error Interrupt signal input.
smpen[4] Signal Master Status of the CPUECTLR.SMPEN bit, whether the processor is SMP enabled.
spiden[4] Signal Slave Secure privileged invasive debug enable.
spniden[4] Signal Slave Secure privileged non-invasive debug enable.
standbywfe[4] Signal Master Indicate if a core is in WFE state.
standbywfi[4] Signal Master Indicate if a core is in WFI state.
standbywfil2 Signal Master Indicate if all the individual processors and the L2 systems are in a WFI state.
ticks[4] InstructionCount Master This port should be connected to one of the two ticks ports on a 'visualization' component, to display a running instruction count.
vcpumntirq[4] Signal Master Virtual processor interface maintenance interrupt request.
vfiq[4] Signal Slave Processor Virtual FIQ signal input.
vinithi[4] Signal Slave Initialize with high vectors enabled after reset.
virq[4] Signal Slave Processor Virtual IRQ signal input.
virtio_s PVBus Slave A model-specific port that connects to virtio peripherals in the L2 system. It ensures coherency, with the correct attributes.
vsei[4] Signal Slave Processor Virtual System Error Interrupt request.

ARMCortexA73xnCT - parameters

This section describes the ARMCortexA73xnCT parameters.

ARMCortexA73xnCT parameters

Table 3-5 ARMCortexA73xnCT parameters

Name Type Allowed values Default value Description
BROADCASTCACHEMAINT bool true, false true Enable broadcasting of cache maintenance operations to downstream caches. The broadcastcachemaint signal overrides this value, if used.
BROADCASTINNER bool true, false true Enable broadcasting of Inner Shareable transactions. The broadcastinner signal overrides this value, if used.
BROADCASTOUTER bool true, false true Enable broadcasting of Outer Shareable transactions. The broadcastouter signal overrides this value, if used.
bus_type uint32_t 0-2 0 Change the reset value of the L2ACTLR register. 0=ACE, 1=CHI, 2=AXI.
CLUSTER_ID uint32_t 0x0-0xFFFF 0x0 Master ID, bits[23:8] of the MPIDR using bits[15:0] of the CLUSTER_ID value.
cpi_div uint32_t 0x1-0x7FFFFFFF 0x1 Divider for calculating Cycles Per Instruction (CPI).
cpi_mul uint32_t 0x1-0x7FFFFFFF 0x1 Multiplier for calculating CPI.
DBGROMADDR uint64_t 0x0-0xffffFFFFffff 0x22000000 Specify bits[43:12] of the top-level ROM table Physical Address.
DBGROMADDRV bool true, false true System samples DBGROMADDR.
dcache-size uint32_t 0x4000-0x100000 0x8000 L1 D-cache size in bytes.
dcache-state_modelled bool true, false false L1 D-cache has stateful implementation. c
GICDISABLE bool true, false true Disable the GIC CPU interface.
icache-state_modelled bool true, false false L1 I-cache has stateful implementation.c
l2cache-size uint32_t 0x0-0x1000000 0x80000 L2 cache size in bytes.
PERIPHBASE uint64_t 0x0-0xFFFFFFFFFFFF 0x13080000 Base address of peripheral memory space, the base address for the GIC CPU Interface registers, sampled into the Configuration Base Address Register (CBAR) at reset.

ARMCortexA73xnCT cache latency cluster parameters

Note

  • These latencies are only effective when you enable cache-state modeling.
  • Timing annotation for transactions downstream of the cache models propagates through the cache models.

Table 3-6 ARMCortexA73xnCT cache latency cluster parameters

Parameter Type Allowed values Default value Description
dcache-maintenance_latency uint64_t - 0x0 L1 D-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
dcache-read_latency uint64_t - 0x0 L1 D-cache timing annotation latency for read accesses, given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-snoop_data_transfer_latency uint64_t - 0x0 L1 D-cache timing annotation latency for received snoop accesses that perform a data transfer, given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-write_latency uint64_t - 0x0 L1 D-cache timing annotation latency for write accesses, given in ticks per byte accessed. For use when dcache-state_modelled=true.
icache-maintenance_latency uint64_t - 0x0 L1 I-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when icache-state_modelled=true.
icache-read_latency uint64_t - 0x0 L1 I-cache timing annotation latency for read accesses, given in ticks per byte accessed. For use when icache-state_modelled=true.
l2cache-maintenance_latency uint64_t - 0x0 L2 cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
l2cache-read_latency uint64_t - 0x0 L2 cache timing annotation latency for read accesses, given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_data_transfer_latency uint64_t - 0x0 L2 cache timing annotation latency for received snoop accesses that perform a data transfer, given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_issue_latency uint64_t - 0x0 L2 cache timing annotation latency for snoop accesses issued by this cache, in total ticks. For use when dcache-state_modelled=true.
l2cache-write_latency uint64_t - 0x0 L2 cache timing annotation latency for write accesses, given in ticks per byte accessed. For use when dcache-state_modelled=true.

ARMCortexA73xnCT core parameters

Table 3-7 ARMCortexA73xnCT core parameters

Named Type Allowed values Default value Description
AA64nAA32 bool true, false true Register width state after reset. true = AArch64, false = AArch32.
CFGEND bool true, false false Endianness configuration after reset. true = big endian, false = little endian.
CFGTE bool true, false false Set to true to take exceptions in T32 state after reset.
CP15SDISABLE bool true, false false Disable write access to some Secure CP15 registers.
CRYPTODISABLE bool true, false false Disable ARMv8 Cryptography Extensions.e
max_code_cache uint32_t 0x1048576-0xFFFFFFFFFFFFF 0x67108864 Maximum number of bytes that are used for caching code translations.
min_sync_level uint32_t 0x0-0x3 0x0 Runtime parameter. Force minimum syncLevel. 0=off=default, 1=syncState, 2=postInsnIO, 3=postInsnAll.
RVBARADDR uint64_t 0x0-0xFFFFFFFFFFFFFFFF 0x0 Reset Vector Base Address when executing in AArch64 state.
semihosting-ARM_SVC uint32_t 0x0-0xFFFFFF 0x123456 A32 SVC number for semihosting.
semihosting-cmd_line string - "" Command line available to semihosting SVC calls.
semihosting-cwd string - "" Default working directory for semihosting.f g
semihosting-enable bool true, false true Enable semihosting SVC traps.
semihosting-heap_base uint32_t 0x0-0xFFFFFFFF 0x0 Virtual address of semihosting heap base.
semihosting-heap_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 Virtual address of the top of the semihosting heap.
semihosting-stack_base uint32_t 0x0-0xFFFFFFFF 0x10000000 Virtual address of the base of descending semihosting stack.
semihosting-stack_limit uint32_t 0x0-0xFFFFFFFF 0x0F000000 Virtual address of semihosting stack limit.
semihosting-Thumb_SVC uint32_t 0x0-0xFF 0xAB T32 SVC number for semihosting.
vfp-enable_at_reset bool true, false false Enable coprocessor access and VFP after reset.
VINITHI bool true, false false Initialize with high vectors enabled after reset.

ARMCortexA73xnCT TLB latency cluster parameters

Table 3-8 ARMCortexA73xnCT TLB latency cluster parameters

Parameter Type Allowed values Default value Description
ptw_latency uint32_t - 0x0 Page table walker latency for Timing Annotation (TA), in simulation ticks.
tlb_latency uint32_t - 0x0 TLB latency for TA, in simulation ticks.
a ARMv8 Cryptography Extensions require a separate package, which is subject to export license conditions. Contact ARM for details.
b The system designer decides whether a debug APB ties the external debug view with other system views. In the model, use a PVBusDecoder to direct traffic to the correct port.
c If either L1 cache is stateful, then the L2 cache is stateful.
d Precede the name with cpun., where n is between 0 and 3.
e ARMv8 Cryptography Extensions require a separate package which is subject to export license conditions. Contact ARM for details.
f The host operating system limits the maximum path length.
g The semihosting-cwd option does not provide any security. Software running on the model can access files outside this directory using relative paths containing .. or using absolute paths.
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