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ARMCortexA7xnCT component

This section describes the ARMCortexA7xnCT component.

ARMCortexA7xnCT - about

This C++ component is a model of r0p0 of the Cortex®-A7 processor containing from one to four cores. The n shows the number of cores.

ARMCortexA7xnCT - ports

This section describes the ports.

Table 3-47 ARMCortexA7xnCT ports

Name Protocol Type Description
axierrirq Signal Master Imprecise aborts from the L2 are signaled by pulsing this pin. Typically this port is connected to an interrupt controller.
broadcastcachemaint Signal Slave Enable broadcasting of cache maintenance operations to downstream caches.
broadcastinner Signal Slave Enable broadcasting of Inner Shareable transactions.
broadcastouter Signal Slave Enable broadcasting of Outer Shareable transactions.
CNTHPIRQ[0-3] Signal Master Hypervisor physical timer event.
CNTPNSIRQ[0-3] Signal Master Non-secure physical timer event.
CNTPSIRQ[0-3] Signal Master Secure physical timer event.
CNTVIRQ[0-3] Signal Master Virtual timer event.
cfgend[0-3] Signal Slave Initialize to BE8 endianness after a reset.
cfgsdisable Signal Slave Disable write access to some GIC registers.
clk_in ClockSignal Slave Main cluster clock input.
clusterid Value Slave Sets the value in the CLUSTERID field (bits[11:8]) of the MPIDR.
cntvalueb CounterInterface Slave Synchronous counter value. This must be connected to the MemoryMappedCounterModule component.
cp15sdisable[0-3] Signal Slave Disable write access to some secure cp15 registers.
cpuporeset[0-3] Signal Slave Power on reset. Initializes all the core logic, including the NEON and VFP logic, Debug, PTM, breakpoint and watchpoint logic in the core CLK domain.
event Signal Peer Event input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENTO signals that are present on hardware.
fiq[0-3] Signal Slave Core FIQ signal input.
irq[0-3] Signal Slave Core IRQ signal input.
irqs[0-223] Signal Slave Shared peripheral interrupts.
l2reset Signal Slave Reset shared L2 memory system, interrupt controller and timer logic.
periphbase Value Slave Base of private peripheral region.
pmuirq[0-3] Signal Master Performance Monitoring Unit (PMU) interrupt signal.
pvbus_m0 PVBus Master AXI bus master channel.
presetdbg Signal Slave Initializes the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
reset[0-3] Signal Slave Core reset signal.
standbywfe[0-3] Signal Master Indicates if a core is in Wait For Event (WFE) state.
standbywfi[0-3] Signal Master Indicates if a core is in Wait For Interrupt (WFI) state.
teinit[0-3] Signal Slave Initialize to take exceptions in T32 state after a reset.
ticks[0-3] InstructionCount Master Core instruction count for visualization.
vfiq[0-3] Signal Slave Core virtual FIQ signal input.
vinithi[0-3] Signal Slave Initialize with high vectors enabled after a reset.
virq[0-3] Signal Slave Core virtual IRQ signal input.
virtio_s PVBus Slave Channel for coherency traffic from virtual model devices. Not for public use.

ARMCortexA7xnCT - parameters

The configuration parameters for this component are set once, irrespective of the number of cores. Each core has its own configuration parameters.

Table 3-48 ARMCortexA7xnCT cluster parameters

Name Type Allowed values Default value Description
CFGSDISABLE Boolean true, false false Disable some accesses to GIC registers.
CLUSTER_ID Integer 0-15 0 Cluster ID value.
dic-spi_count Integer 0-480, in increments of 32 64 Number of shared peripheral interrupts implemented.
internal_vgic Boolean true, false true Configures whether or not the model of the cluster contains a VGIC.
l1_dcache-state_modelled Boolean true, false false Set whether or not L1 D-cache has stateful implementation.
l1_icache-state_modelled Boolean true, false false Set whether or not L1 I-cache has stateful implementation.
l2_cache-size Integer 0 (no L2 cache), 128KB, 256KB, 512KB, 1024KB 0x800000 Set L2 cache size in bytes.
l2_cache-state_modelled Boolean true, false false Set whether or not L2 cache has stateful implementation.
PERIPHBASE Integer 0x0000000000-0xFFFFFFFFFF 0x13080000a Base address of peripheral memory space.

Table 3-49 ARMCortexA7xnCT core parameters

Name Type Allowed values Default value Description
ase-presentb Boolean true, false true Set whether or not CT model has been built with NEON™ support.
CFGEND Boolean true, false false Initialize to BE8 endianness.
CP15SDISABLE Boolean true, false false Initialize to disable access to some CP15 registers.
cpi_mul Integer 1-0x7FFFFFFF 1 Multiplier for calculating CPI.
cpi_div Integer 1-0x7FFFFFFF 1 Divider for calculating Cycles Per Instruction (CPI).
DBGROMADDR Integer 0x00000000-0xFFFFFFFF 0x12000003 This value is used to initialize the CP15 DBGDRAR register. Bits[39:12] of this register specify the ROM table physical address.
DBGROMADDRV Boolean true, false true If true, this sets bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid.
DBGSELFADDR Integer 0x00010003 0x00010003 This value is used to initialize the CP15 DBGDSAR register. Bits[39:17] of this register specify the ROM table physical address.
DBGSELFADDRV Boolean true, false true If true, this sets bits[1:0] of the CP15 DBGDSAR to indicate that the address is valid.
l1_dcache-size Integer 0x2000-0x10000 0x8000 Size of L1 D-cache.
l1_icache-size Integer 0x2000-0x10000 0x8000 Size of L1 I-cache.
min_sync_level Integer 0-3 0 Controls the minimum syncLevel.
semihosting-cmd_line String No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable Boolean true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-ARM_SVC Integer 0x000000-0xFFFFFF 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC Integer 0x00-0xFF 0xAB T32 SVC number for semihosting.
semihosting-heap_base Integer 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit Integer 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base Integer 0x00000000-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit Integer 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of stack limit.
TEINIT Boolean true, false false T32 exception enable. The default has exceptions including reset handled in A32 state.
vfp-enable_at_resetc Boolean true, false false Enable coprocessor access and VFP at reset.
vfp-presentb Boolean true, false true Set whether or not CT model has been built with VFP support.
VINITHI Boolean true, false false Initialize with high vectors enabled.

ARMCortexA7xnCT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the coprocessor 14 registers and the integration and test registers.

ARMCortexA7xnCT - caches

This component implements the L1 and L2 caches as architecturally defined.

ACE limitation

AXI Coherency Extensions (ACE) are extensions to AXI4 that support system-level cache-coherency between multiple clusters. The ACE cache models in the Cortex-A15 and the Cortex-A7, and the ACE support in the CCI-400 have a limitation: these functional models process only one transaction at a time. Normally, the simulation processes each transaction to completion before allowing any master to generate another transaction. However, there is a situation in which the simulation might fail. Suppose a SystemC bus slave calls wait() while it is processing a transaction. This call might allow another master to issue another transaction that passes through the CCI-400 or the Cortex-A15/Cortex-A7 caches. This situation could happen if a SystemC bus master running in another thread is connected to one of the ACE-lite ports on the CCI-400.

Cache and TLB component visibility

If a core model has a cache model available, to create it and make it visible, enable it. To enable the cache model and be ready to use cache CADI, set these model parameters:

  • l1_icache-state_modelled
  • l1_dcache-state_modelled
  • l2_cache-state_modelled

To use cache and TLB viewers, connect the cache and TLB CADI components.

ARMCortexA7xnCT - debug features

This component exports a CADI debug interface.

ARMCortexA7xnCT - debug - registers

All core, VFP, CP14, and CP15 registers are visible in the debugger. All CP14 debug registers are implemented.

ARMCortexA7xnCT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexA7xnCT - debug - memory

This component presents three 4GB views of virtual address space: hypervisor, secure, and non-secure.

ARMCortexA7xnCT - verification and testing

This component passes tests using the architecture validation suite tests, booting Linux on an example system containing an ARMCortexA7xnCT component, and booting Linux on an example system containing an ARMCortexA7xnCT component and an ARMCortexA15xnCT Cache Coherent Interconnect (CCI400) model.

ARMCortexA7xnCT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • The GIC does not respect the CFGSDISABLE signal. This leads to some registers wrongly being accessible.
  • The Broadcast Translation Lookaside Buffer (TLB) or cache operations in this model do not cause other cores in the cluster that are asleep because of Wait For Interrupt (WFI) to wake up.
  • It ignores the RR bit in the SCTLR.
  • It implements the Power Control Register in the system control coprocessor but writing to it does not change the behavior of the model.
  • It does not implement ETM registers.
  • It does not support the Cortex-A7 mechanism to read the internal memory that the Cache and TLB structures use through the implementation defined region of the system coprocessor interface.
a If you are using the ARMCortexA7xnCT component on a VE model platform, this parameter is set automatically to 0x2C000000 and is not visible in the parameter list.
b The ase-present and vfp-present parameters configure the synthesis options.
vfp present and ase present
NEON and VFPv4-D32 supported.
vfp present and ase not present
VFPv4-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv4-D32 support.
vfp not present and ase not present
Model has neither NEON nor VFPv4-D32 support.
c This is a model-specific behavior with no hardware equivalent.
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