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This section describes component port declarations.
About component port declarations
Communication between components is done with master and slave ports using Transaction Level Modeling (TLM). The ports use standard protocols or protocols you define to communicate between components. Read and write accesses are always initiated from master ports.
A LISA+ component can contain arrays of ports, for example multiple interrupt ports in an IRQ controller.
Internal ports are: normal ports that are not accessible from outside of the component, not visible in the component, not a part of the component interface, an internal implementation detail of a component.