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About component port declarations

Communication between components is done with master and slave ports using Transaction Level Modeling (TLM). The ports use standard protocols or protocols you define to communicate between components. Read and write accesses are always initiated from master ports.

The processors use these interfaces to communicate with the peripherals. Peripherals can use them to communicate with each other. The communication connections are defined in the connection section of each component.

This kind of communication encapsulates each component behind an abstract interface. Components can easily replace each other, and it is generally easier to modify the structure of a system and to reuse components in other systems.

Components must interact during the simulation and this communication must be based on a defined protocol. LISA+ has the ability to define customized protocols that are tailored to the specific components and offer a clean interface. Ports of components can only be connected if they implement the same protocol.

A port declaration has the format:

port_attributes port<protocol_name> instanceName[, instanceName2 …];
a combination of the attributes master, slave, internal and addressable.
the name of a protocol. In a sense, a port type.

If a port has behavior that implements one or more protocol functions, the port declaration also has a body containing behavior declarations:

port_attributes port<protocol_name> instanceName
    behavior f {    }
    behavior g {    }
    // …