If enabled, this source traces all writes to the processor registers.
This trace source includes writes to core registers R0 to R14, CPSR and SPSR, VFP registers such as S0 to S31, D0 to D31, FPSCR, FPEXC, and writes to CP14 and CP15 registers. Banked registers are traced separately using the mode as a suffix to the register name, for example r13 (current register R13) and r13_mon (banked register R13).
<time> <scale> R <register> <value>
Timestamp (decimal value).
<time>. This gives consistency with device-specific Tarmac Trace formats.
Register name in lowercase letters. Banked core registers can have a mode appended with a single underscore. Banked CP14/CP15 registers have
_nsappended to indicate access of either the secure or non-secure banked register.
Hexadecimal value written to the register (64 bits maximum).