Debug Reset Control and Reset Schedule Registers
The debug reset control and schedule registers are used together to reset some or all of the system.
The following tables show the bit assignments of the Debug Reset Control and Reset Schedule registers.
|||SYS_DBGRST||RW||Schedule a debug system reset when 1.|
|||SYS_PORESET||RW||Schedule a system-wide power-on reset when 1.|
|||CLUSTER1_SCURESET||RW||Schedule Cortex-A7 core resets. These fields exhibit the same behavior as the Cortex-A15 reset fields.|
Schedule Cortex-A15 resets. When a field is 1, a reset pulse is scheduled for when the RST_SCHED timer expires.
NoteIf the Cortex-A15 cluster is configured to contain fewer than four cores, then the high-order bits of each field corresponding to unimplemented cores are RAZ/WI.
|||DISABLE||RW||Disables the reset scheduler timer. This bit auto-sets when the TIMER field reaches zero.|
|[7:0]||TIMER||RW||Reset schedule timer. This field auto-decrements if the DISABLE field is 0. When the timer reaches zero, the interrupts configured in the RST_CTRL register are pulsed. Writing 0 to this field, and 0 to the DISABLE field pulses the interrupts immediately.|
To use the registers:
- Write 1 to each bit of the RST_CTRL register that corresponds to the reset that is to be pulsed.
- Write a value to the TIMER field of the RST_SCHED register. If the DISABLE bit is written as 0, or if it is already 0, the timer automatically begins to decrement. When the TIMER reaches zero, any resets that are scheduled in the RST_CTRL register are asserted, and the DISABLE field resets to 1 to prevent subsequent resets.
- Writing 0 to the TIMER field causes the resets to be pulsed immediately, if the DISABLE field is 0.
If the TIMER field of the RST_SCHED register is written together with a value of 0 in the DISABLE field in a single transaction, then the reset scheduler activates immediately. Otherwise, the TIMER only decrements when 0 is written to the DISABLE field later.