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Reset hold registers, RST_HOLD0 and RST_HOLD1

The reset hold registers enable a processor to place any core or cluster into a reset state.

The reset is scheduled for when the core to be reset enters the STANDBYWFI state, and remains in reset until another core brings it out of reset.

The following reset hold registers exist:

RST_HOLD0
Toggles resets for the Cortex-A15 cluster.
RST_HOLD1
Toggles resets for the Cortex-A7 cluster.

The following table shows the bits in the RST_HOLDx registers that force a particular reset.

For all supported resets, the reset is held for as long as the corresponding bit in the RST_HOLDx register is HIGH.

Table 1. RST_HOLDx register bit assignments
Bits Name Type Description
[8] CLUSTER_RESET RW Write 1 to this bit to reset the entire cluster. The reset is scheduled to occur when every core in the cluster has entered the STANDBYWFI state. The cluster is then held in reset until 0 is written to the field. A cluster reset places each core into a power-on reset and resets the interrupt controller and L2 logic.
[7:4] CPU_PORESET RW Write 1 to bit n to assert a core power-on reset for core n. The reset is scheduled to occur when core n enters the STANDBYWFI state. The reset line is then held indefinitely until 0 is written to the field. A core power-on reset resets the core logic, NEON/VFP and debug logic.
[3:0] CPU_RESET RW Write 1 to bit n to assert a core reset for core n. The reset is scheduled to occur when core n enters the STANDBYWFI state. The reset line is then held indefinitely until 0 is written to the field. A core reset resets the core logic and NEON/VFP.