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Timing considerations

The Fixed Virtual Platforms provide environments that enable you to run software applications in a functionally-accurate simulation.

However, because of the relative balance of fast simulation speed compared to timing accuracy, situations exist where the models might behave unexpectedly. When code interacts with real world devices such as timers and keyboards, data arrives in the modeled device in real world, or wall clock, time, but simulation time can be running much faster than the wall clock.

This means that a single key-press might be interpreted as several repeated key presses, or a single mouse click is incorrectly interpreted as a double click. The VE FVPs provide the Rate Limit feature to match simulation time to wall-clock time. Enabling Rate Limit, either by using the Rate Limit button in the CLCD display, or the rate_limit-enable model instantiation parameter, forces the model to run at wall clock time. This avoids issues with two clocks running at significantly different rates. For interactive applications, ARM recommends enabling Rate Limit.