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Software Reset Register, SYS_SWRESET

Use the Software Reset Register to reset the system from a given level.

See Reset architecture for information about reset levels in the system. The resets are applied, then automatically released. The following table shows the bit assignments for the software reset register.

Table 1. SYS_SWRESET Register bit assignments
Bits Name Type Description
[23:20] CORES1 WO

Defines the cores in the Cortex-A7 cluster to reset when LEVEL is set to 1 and CLUSTER_LEVEL0 is set to 00 or 01. One bit exists for each core. A core is reset if the corresponding bit is 1.

Note

If fewer than four cores are implemented in a cluster, then the higher order bits are ignored.
[19:16] CORES0 WO

Defines the cores in the Cortex-A15 cluster to reset when LEVEL is set to 1 and CLUSTER_LEVEL0 is set to 00 or 01. One bit exists for each core. A core is reset if the corresponding bit is 1.

Note

If fewer than four cores are implemented in a cluster, then the higher order bits are ignored.
[15:12] - - -
[11:10] CLUSTER_LEVEL1 WO

For a Cortex-A7 cluster reset, defines the reset level:

00
Individual core reset.
01
Individual core power-on-reset.
10
Full cluster reset.
11
Reserved.
[9:8] CLUSTER_LEVEL0 WO

For a Cortex-A15 cluster reset, defines the reset level:

00
Individual core reset.
01
Individual core power-on-reset.
10
Full cluster reset.
11
Reserved.
[7:6] - - -
[5:4] CLUSTERS WO

Enables reset for each cluster when LEVEL is set to a cluster reset:

Bit[4]
Set to 1 to reset the Cortex-A15 cluster.
Bit[5]
Set to 1 to reset the Cortex-A7 cluster.
[3] - - -
[2] SWRESET WO Write 1 to apply the software reset.
[1] - - This bit is reserved for future reset levels.
[0] LEVEL WO

Choose what to reset:

0
System reset. Resets the system and both clusters.
1
Core or cluster reset. Resets the clusters and cores specified in the CLUSTERS field.

Writing to SYS_SWRESET forms a request to the reset controller that is serviced as soon as possible.

Writing to SYS_SWRESET while an operation is already in progress modifies that operation as far as possible. Any resets that have not been asserted are no longer asserted, but resets that have been asserted already remain active for at least 16 clock cycles.