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Dual Cluster System Configuration Block

The Dual Cluster System Configuration Block (DCSCB) provides basic functionality for controlling clocks, resets, and configuration pins in the dual cluster system.

It is not intended to provide the complete trick-box functionality that is found in a typical top-level simulation test-bench. Instead, its main use is to form the programming interface for the clock, power, and reset controllers so that software can implement the ARM big.LITTLE™ switching. The following table shows the DCSCB registers, that this section describes. The DCSCB occupies a 4kB region of memory in the range 0x10020000-0x10020FFF, and any accesses to undefined areas of this address space result in an error response. The registers are divided into the following categories:

  1. The system control registers are identical across all platform implementations of the dual cluster system. They control system-level functions such as the resets of individual cores and clusters.
  2. The platform control registers provide a common model for controlling and reading platform-level configuration options for the dual cluster system implementation. Some platform implementations might support only a subset of these registers. The definitions and address offsets of these registers are based on the Versatile Express daughter-card configuration controller command codes.

Note

  • All registers are word-sized and only support word-sized transactions.
  • Reads from write-only registers or fields return zero.
  • Some registers do not implement all 32 bits. See the Width column of the following table.
  • Unimplemented bits are RAZ/WI.

The following table shows the DCSCB System Control Registers.

Table 3-23 DCSCB System Control Registers

Name Offset Type Width Reset Description
RST_HOLD0 0x000 RW 9 0x00000000 or 0x000001001 Holds the selected resets in the Cortex-A15 cluster.
RST_HOLD1 0x004 RW 9 0x00000000 or 0x000001001 Holds the selected resets in the Cortex-A7 cluster.
SYS_SWRESET 0x008 WO 24 0x00000000 or 0x000001001 Asserts a software reset of the system.
RST_STAT0 0x00C RO 9 0x00000000 or 0x000001001 Determines the Cortex-A15 processor resets that are asserted.
RST_STAT1 0x010 RO 9 0x00000000 or 0x000001001 Determines the Cortex-A7 processor resets that are asserted.
CLUSTER0_CFG_R 0x020 RO 20 - Current configuration of the static configuration input pins of the Cortex-A15 processor.
CLUSTER0_CFG_W 0x024 RW 20 0x00000000 Configuration of the static configuration input pins of the Cortex-A15 processor at the next reset.
CLUSTER1_CFG_R 0x028 RO 20 - Current configuration of the static configuration input pins of the Cortex-A7 processor.
CLUSTER1_CFG_W 0x02C RW 20 0x00010000 Configuration of the static configuration input pins of the Cortex-A7 processor at the next reset.
DCS_CFG_R 0x030 RO 2 - Reads the power-on configuration of system-level configuration pins.

The following table shows the DCSCB Platform Control Registers.

Table 3-24 DCSCB Platform Control Registers

Name Offset Type Width Reset Description
DCS_LEDS 0x104 RW 8 0x00000000 Controls platform LEDS or other platform-specific indication methods.
DCS_SW 0x108 RO 8 0x00000000 Reads the value of platform switches or other platform-specific configuration methods.

The following table shows the DCSCB Interrupt Generator Registers.a

Table 3-25 DCSCB Interrupt Generator Registers

Name Offset Type Width Reset Description
INT_CTRL 0x120 RW 2 0x00000000 Controls generation of interrupts from the interrupt generation trickbox.
INT_FREQ 0x124 RW 10 0x00000000 Controls the frequency of timer-generated interrupts.
INT_TYPE0 0x130 RW 32 0x00000000 Configures the interrupt generator to use level or edge-triggered interrupts for each interrupt line.
INT_TYPE1 0x134 RW 32 0x00000000 Configures the interrupt generator to use level or edge-triggered interrupts for each interrupt line. If the interrupt generator implements fewer than the maximum 128 interrupts, higher order registers corresponding to unimplemented interrupts are RAZ/WI.
INT_TYPE2 0x138 RW 32 0x00000000
INT_TYPE3 0x13C RW 32 0x00000000
INT_GENERATE 0x140 WO 1 - Generates the next interrupt.
INT_NUMBER 0x144 RO 8 0x00000000 Number of the next interrupt.
INT_ACK 0x148 WO 1 - Acknowledges all the generated interrupts.
INT_SEQ0 – INT_SEQ127 0x200-0x3FC RW 7 0x00000000 Sequence number for all generated interrupts.

The following table shows the DCSCB ID Registers.

Table 3-26 DCSCB ID Registers

Name Offset Type Width Reset Description
DCS_AID 0xFF8 RO 32 - Dual Cluster System auxiliary platform ID register.
DCS_ID 0xFFC RO 32 - Dual Cluster System platform ID register.

The following table shows the DCSCB Debug Control Registers.

Table 3-27 DCSCB Debug Control Registers

Name Offset Type Width Reset Description
DBG_RST_CTRL 0x520 RW 32 0x00000000 Debugger reset control register that defines the resets to assert. This register is intended for debug access only. Although software running on the system can currently access it, this might change in the future.
DBG_RST_SCHED 0x018 RW 9 0x00000100 Debugger reset schedule register to control when to assert resets. This register is intended for debug access only. Although software running on the system can currently access it, this might change in the future.

This section contains the following subsections:

a Interrupt generator registers are RAZ/WI if the interrupt generator is not present.
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