Dual Cluster System Configuration Block
The Dual Cluster System Configuration Block (DCSCB) provides basic functionality for controlling clocks, resets, and configuration pins in the dual cluster system.
It is not intended to provide the complete trick-box functionality that is
found in a typical top-level simulation test-bench. Instead, its main use is to form the
programming interface for the clock, power, and reset controllers so that software can
implement the ARM big.LITTLE™ switching. The following table shows the
DCSCB registers, that this section describes. The DCSCB occupies a 4kB region of memory in the
0x10020FFF, and any accesses to undefined areas of this address
space result in an error response. The registers are divided into the following
- The system control registers are identical across all platform implementations of the dual cluster system. They control system-level functions such as the resets of individual cores and clusters.
- The platform control registers provide a common model for controlling and reading platform-level configuration options for the dual cluster system implementation. Some platform implementations might support only a subset of these registers. The definitions and address offsets of these registers are based on the Versatile Express daughter-card configuration controller command codes.
- All registers are word-sized and only support word-sized transactions.
- Reads from write-only registers or fields return zero.
- Some registers do not implement all 32 bits. See the Width column of the following table.
- Unimplemented bits are RAZ/WI.
The following table shows the DCSCB System Control Registers.
Table 3-23 DCSCB System Control Registers
||Holds the selected resets in the Cortex-A15 cluster.|
||Holds the selected resets in the Cortex-A7 cluster.|
||Asserts a software reset of the system.|
||Determines the Cortex-A15 processor resets that are asserted.|
||Determines the Cortex-A7 processor resets that are asserted.|
||RO||20||-||Current configuration of the static configuration input pins of the Cortex-A15 processor.|
||Configuration of the static configuration input pins of the Cortex-A15 processor at the next reset.|
||RO||20||-||Current configuration of the static configuration input pins of the Cortex-A7 processor.|
||Configuration of the static configuration input pins of the Cortex-A7 processor at the next reset.|
||RO||2||-||Reads the power-on configuration of system-level configuration pins.|
The following table shows the DCSCB Platform Control Registers.
Table 3-24 DCSCB Platform Control Registers
||Controls platform LEDS or other platform-specific indication methods.|
||Reads the value of platform switches or other platform-specific configuration methods.|
The following table shows the DCSCB Interrupt Generator Registers.a
Table 3-25 DCSCB Interrupt Generator Registers
||Controls generation of interrupts from the interrupt generation trickbox.|
||Controls the frequency of timer-generated interrupts.|
||Configures the interrupt generator to use level or edge-triggered interrupts for each interrupt line.|
||Configures the interrupt generator to use level or edge-triggered interrupts for each interrupt line. If the interrupt generator implements fewer than the maximum 128 interrupts, higher order registers corresponding to unimplemented interrupts are RAZ/WI.|
||WO||1||-||Generates the next interrupt.|
||Number of the next interrupt.|
||WO||1||-||Acknowledges all the generated interrupts.|
|INT_SEQ0 â€“ INT_SEQ127||
||Sequence number for all generated interrupts.|
The following table shows the DCSCB ID Registers.
Table 3-26 DCSCB ID Registers
||RO||32||-||Dual Cluster System auxiliary platform ID register.|
||RO||32||-||Dual Cluster System platform ID register.|
The following table shows the DCSCB Debug Control Registers.
Table 3-27 DCSCB Debug Control Registers
||Debugger reset control register that defines the resets to assert. This register is intended for debug access only. Although software running on the system can currently access it, this might change in the future.|
||Debugger reset schedule register to control when to assert resets. This register is intended for debug access only. Although software running on the system can currently access it, this might change in the future.|
This section contains the following subsections: