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Cortex-A7 static configuration read and write Registers

The Cortex-A7 static configuration read and write registers determine and control the values driven onto the static configuration input pins of Cortex-A7.

The behavior of these registers is the same as the Cortex-A15 static configuration read and write registers. See 3.21.3 Reset Status Registers, RST_STAT0 and RST_STAT1 for information.

The following table shows the bit assignments for both registers.

Table 3-34 CLUSTER1_CFG_R and CLUSTER1_CFG_W Register bit assignments

Bits Name CLUSTER1_CONFIG_R Access CLUSTER1_CONFIG_W Access Description
[19:16] CLUSTER1_CLUSTERID RO RW The value driven onto the CLUSTERID static input pins.
[15:12] - RAZ RAZ/WI Reserved.
[11:8] CLUSTER1_TEINIT RO RW The value driven onto the TEINIT static input pins. One bit exists for each core in the cluster.
[7:4] CLUSTER1_VINITHI RO RW The value driven onto the VINITHI static input pins. One bit exists for each core in the cluster.
[3:0] CLUSTER1_CFGEND RO RW The value driven onto the CFGEND static input pins. One bit exists for each core in the cluster.

The default values of the Cortex-A7 static configuration registers:

  • Set the exception endianness to little-endian for every core.
  • Disable high exception vectors for every core, that is, exception vectors start at address 0x00000000.
  • Disable Thumb exceptions for every core, that is, exceptions are entered in ARM state.
  • Do not prevent write access to secure CP15 registers.
  • Set the cluster ID to 0x1.
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