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Reset architecture

The platform layer defines several levels of reset.

The following levels of reset exist, in increasing order:

Core reset
Core reset, including NEON and VFP.
Core power-on reset
Core, NEON, VFP, and CPU debug.
Cluster reset
Entire core cluster including L2 and interrupt controller.
System reset
Cluster reset for all clusters plus dual cluster system.
Power-on reset
Entire system and platform including the debug subsystem.

Debug resets

The processors contain the following debug-related reset signals:

nDBGRESET[n:0]
Where n is the number of cores in the cluster.
nPRESETDBG
In the Cortex-A7, this reset only exists at the integration layer, that integrates the CoreSight subsystem. Conversely, the Cortex-A15 processor integrates the CoreSight components at the Cortex-A15 level and therefore contains the nPRESETDBG signal.

nDBGRESET[n:0] resets the debug logic for each core, including breakpoint and watchpoint logic. nPRESETDBG resets the CoreSight debug subsystem, including the CTIs, CTMs, and debug APB. A core power-on reset, cluster reset, and system reset assert the nDBGRESET lines to the appropriate cores, but only a power-on reset asserts nPRESETDBG. All components in the CoreSight debug subsystem are in the same nPRESETDBG domain and cannot be reset independently of each other.

Each successive reset level from the list above is a superset of the previous reset level, so a reset level also resets everything in the levels below it.

For example, a core power-on reset includes everything that is reset by a core reset, and a system reset includes a cluster reset, core power-on reset, and core reset for each cluster. A memory-mapped register can explicitly control platform resets, but the reset controller also manages platform resets. The reset controller is closely coupled with the power controller.

See 3.21.1 Reset hold registers, RST_HOLD0 and RST_HOLD1 and 3.21.2 Software Reset Register, SYS_SWRESET for information about the reset registers.

At power-on, the dual cluster system platform issues a complete power-on reset to reset:

  • Core clusters.
  • Interconnect.
  • Debug.
  • Peripherals.

When the power-on reset sequence is complete, a static configuration option determines whether the Cortex-A7 cluster or the Cortex-A15 cluster, or both, exit reset.

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