Restrictions on the processor models
Separate documentation contains detailed information regarding the features that are not fully implemented in the processor models that are included with the VE Fixed Virtual Platforms (FVPs). See the Fast Models Reference Manual.
The following general restrictions apply to the FVP implementations of ARM processors:
- The simulator does not model cycle timing. In aggregate, all instructions execute in one core master clock cycle, with the exception of Wait For Interrupt.
- Write buffers are not modeled.
- Most aspects of Translation Lookaside Buffer (TLB) behavior are implemented in the models. Architecture v7 models use the TLB memory attribute settings when you enable stateful cache.
- No MicroTLB is implemented.
- A single memory access port is implemented. The port combines accesses for:
Configuration of the peripheral port memory map register is ignored.
- All memory accesses are atomic and are performed in programmers view order. All transactions on the PVBus are a maximum of 32 bits wide. Unaligned accesses are always performed as byte transfers.
- Some instruction sequences are executed atomically, ahead of the component master clock, so that system time advances during their execution. This can sometimes have an effect in sequential access of device registers where devices expect time to progress between each access.
- Interrupts are not taken at every instruction boundary.
- The semihosting-debug configuration parameter is ignored.
- Integration and test registers are not implemented.
- Not all CP14 debug registers are implemented.
- You must use an external debugger to debug an FVP.
- The model supports the following breakpoint types:
- Single address unconditional instruction breakpoints.
- Single address unconditional data breakpoints.
- Unconditional instruction address range breakpoints.
- Pseudo-registers in the debugger support processor exception breakpoints. Setting an exception register to a non-zero value stops execution on entry to the associated exception vector.
- Performance counters are not implemented.