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Bus consistency messages

Checkers monitor for suspicious interactions between conflicting memory attributes and cache and Translation Lookaside Buffer (TLB) maintenance operations.

These checkers print messages on stderr. You must launch the model from the command line to observe these messages.

The FASTSIM_PVCACHE_VERBOSE environment variable controls the checkers and you can set its value as follows:

0

Does not display consistency messages. This is the default behavior if FASTSIM_PVCACHE_VERBOSE is not set.

1

Only displays severe errors.

2 or higher

Displays both severe errors and warnings.

The checkers within the model monitor for the following:

  • Multiple entries in the cache with the same security world.

    A Secure and a Non-secure line in the cache and at least one of them is dirty.

  • Mismatched attributes.

    Mixed attributes for a particular physical address, that is UNPREDICTABLE in the architecture.

  • Cache Coherent Interconnect snoop or DVM enables.

    Misuses of the Cache Coherent Interconnect during snoop or DVM enables or disables.

  • Snoop or DVM messages received while in reset.

    A snoop or DVM request is sent to a core in reset. This could deadlock the hardware.

  • Invalidation of Dirty lines.

    A cache is invalidated with dirty lines.

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