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Cortex®‑A15 static configuration read and write Registers

The Cortex®‑A15 static configuration read and write registers provide a method to observe and change the values driven onto the static configuration input pins of the Cortex‑A15 processor.

The static configuration inputs must only be changed when the processor is under reset. Therefore, the following registers control and observe the values:

  • The read-only static configuration read register shows the values currently driven onto the static input pins.
  • The read and write static configuration write register contains the value that is to be driven onto the static configuration inputs when the processor is next reset.

When the processor is reset, the contents of the CLUSTER0_CFG_W register are copied to the CLUSTER0_CFG_R register, and this drives the static configuration input pins. The following table shows the bit assignments for the registers. Both registers contain the same bit fields. Only the access type is different.

Table 3-33 CLUSTER0_CFG_R and CLUSTER0_CFG_W Register bit assignments

Bits Name CLUSTER0_CONFIG_R Access CLUSTER0_CONFIG_W Access Description
[19:16] CLUSTER0_CLUSTERID RO RW The value driven onto the CLUSTERID static input pins.
[15:13] - RAZ RAZ/WI Reserved.
[12] CLUSTER0_IMINLN RO RW The value of the IMINLN static input pin.
[11:8] CLUSTER0_CFGTE RO RW The value driven onto the CFGTE static input pins. One bit exists for each core in the cluster.
[7:4] CLUSTER0_VINITHI RO RW The value driven onto the VINITHI static input pins. One bit exists for each core in the cluster.
[3:0] CLUSTER0_CFGEND RO RW The value driven onto the CFGEND static input pins. One bit exists for each core in the cluster.

The default values of the Cortex‑A15 static configuration registers:

  • Set the exception endianness to little-endian for every core.
  • Disable high exception vectors for every core, that is, exception vectors start at address 0x00000000.
  • Disable Thumb® exceptions for every core, that is, exceptions are entered in ARM state.
  • Do not prevent write access to secure CP15 registers.
  • Set the cluster ID to 0x0.
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