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Interrupt Generator Sequencing Registers, INT_SEQx

The interrupt generator sequencing registers configure the sequence for trickbox-generated interrupts.

You must program these registers with a valid sequence before enabling the interrupt generator. There are up to 128 INT_SEQx registers, one for each supported interrupt.

If the interrupt generator supports fewer than the maximum 128 interrupts, then registers corresponding to unavailable interrupts are RAZ/WI.

If the interrupt generator is not present, all registers are RAZ/WI.

Each INT_SEQx register has the bit assignment that the following table shows. INT_SEQx configures the interrupt line that is asserted when the xth interrupt is requested.

The following table shows the bit assignments for the INT_SEQx register.

Table 3-44 INT_SEQx Register bit assignments

Bits Name Type Description
[6:0] NUMBER RW Configures the interrupt line that is to be asserted for this position in the sequence. If the interrupt generator is configured to support fewer than 128 interrupts, then the higher-order bits of this field are RAZ/WI. The width of the field is log2(Number of supported interrupts).

Before generation starts, the NUMBER field of every INT_SEQx register must be unique, otherwise results are UNPREDICTABLE. Writing to these registers when interrupt generation is enabled, or with unacknowledged interrupts, gives UNPREDICTABLE behavior. If the interrupt generator is configured to support fewer than 128 interrupts, then the registers corresponding to the unavailable interrupts are RAZ/WI.

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