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Software Reset Register, SYS_SWRESET

Use the Software Reset Register to reset the system from a given level.

See 3.22 Reset architecture for information about reset levels in the system. The resets are applied, then automatically released. The following table shows the bit assignments for the software reset register.

Table 3-30 SYS_SWRESET Register bit assignments

Bits Name Type Description
[23:20] CORES1 WO

Defines the cores in the Cortex®‑A7 cluster to reset when LEVEL is set to 1 and CLUSTER_LEVEL0 is set to 0b00 or 0b01. One bit exists for each core. A core is reset if the corresponding bit is 1.

Note:

If fewer than four cores are implemented in a cluster, then the higher order bits are ignored.
[19:16] CORES0 WO

Defines the cores in the Cortex‑A15 cluster to reset when LEVEL is set to 1 and CLUSTER_LEVEL0 is set to 0b00 or 0b01. One bit exists for each core. A core is reset if the corresponding bit is 1.

Note:

If fewer than four cores are implemented in a cluster, then the higher order bits are ignored.
[15:12] - - -
[11:10] CLUSTER_LEVEL1 WO

For a Cortex‑A7 cluster reset, defines the reset level:

0b00 Individual core reset.
0b01 Individual core power-on-reset.
0b10 Full cluster reset.
0b11 Reserved.
[9:8] CLUSTER_LEVEL0 WO

For a Cortex‑A15 cluster reset, defines the reset level:

0b00 Individual core reset.
0b01 Individual core power-on-reset.
0b10 Full cluster reset.
0b11 Reserved.
[7:6] - - -
[5:4] CLUSTERS WO

Enables reset for each cluster when LEVEL is set to a cluster reset:

Bit[4] Set to 1 to reset the Cortex‑A15 cluster.
Bit[5] Set to 1 to reset the Cortex‑A7 cluster.
[3] - - -
[2] SWRESET WO Write 1 to apply the software reset.
[1] - - This bit is reserved for future reset levels.
[0] LEVEL WO

Choose what to reset:

0 System reset. Resets the system and both clusters.
1 Core or cluster reset. Resets the clusters and cores specified in the CLUSTERS field.

Writing to SYS_SWRESET forms a request to the reset controller that is serviced as soon as possible.

Writing to SYS_SWRESET while an operation is already in progress modifies that operation as far as possible. Any resets that have not been asserted are no longer asserted, but resets that have been asserted already remain active for at least 16 clock cycles.

Writing to SYS_SWRESET

When a reset is requested using SYS_SWRESET:

  • A core reset is only asserted when that core has entered the STANDBYWFI state.
  • A cluster reset is only asserted when all cores in the cluster have entered a STANDBYWFI state.
  • If a reset request applies to more than one core, the resets of the core might be applied at different times depending on when they each enter the STANDBYWFI state.
  • The resets are all released simultaneously.
  • Resets are asserted for a minimum of 16 clock cycles.
  • A complete system reset does not wait for any STANDBYWFI signals to be asserted.

Software sequence to assert reset using SYS_SWRESET

For core A to reset Core B, software must perform the following actions:

Note:

Core A and core B can be the same core.
  1. Core A writes to the appropriate SYS_SWRESET fields to request the reset of core B or its cluster.
  2. Core B programs the GIC of its cluster to prevent IRQs and FIQs being asserted to Core B.
  3. Core B executes a WFI. After Core B executes WFI, its STANDBYWFI output goes HIGH. At this point, the reset controller asserts reset for a minimum of 16 cycles and then de-asserts it.

Interaction with RST_HOLDx

The SYS_SWRESET and RST_HOLDx registers operate independently.

Resetting a core or cluster using SYS_SWRESET does not cause any resets that are held using RST_HOLDx to be released. However, using SYS_SWRESET to assert a complete system reset resets all DCSCB registers to their default values, including RST_HOLDx. This means that clusters that are held in reset might be released, depending on the value of the CFG_ACTIVECLUSTER input.

The following table shows the components that are reset depending on the values written to the SYS_SWRESET register. In the table, the symbols w, x, y, and z each represent a logic 1 or 0. A dash represents a don't care value.

Table 3-31 Components reset depending on values written to SYS_SWRESET register

LEVEL 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CLUSTERS - 00 01 01 01 10 10 10 11 11 11 11 11 11 11 11 11
CLUSTER_LEVEL0 - - 00 01 10 - - - 00 01 10 00 01 10 00 01 10
CLUSTER_LEVEL1 - - - - - 00 01 01 00 00 00 01 01 01 10 10 10
CORES0 - - abcd abcd abcd - - - abcd abcd - abcd abcd - abcd abcd -
CORES1 - - - - - wxyz wxyz wxyz wxyz wxyz wxyz wxyz wxyz wxyz - - -
Cortex-A15 core 0 reset - - d d d - - - d d - d d - d d -
Cortex-A15 core 1 reset - - c c c - - - c c - c c - c c -
Cortex-A15 core 2 reset - - b b b - - - b b - b b - b b -
Cortex-A15 core 3 reset - - a a a - - - a a - a a - a a -
Cortex-A15 core 0 PORESET - - - d d - - - - d - - d - - d -
Cortex-A15 core 1 PORESET - - - c c - - - - c - - c - - c -
Cortex-A15 core 2 PORESET - - - b b - - - - b - - b - - b -
Cortex-A15 core 3 PORESET - - - a a - - - - a - - a - - a -
Cortex-A15 cluster reset - - - - - - - - - - - - - - - -
Cortex-A7 core 0 reset - - - - - z z z z z z z z z - - -
Cortex-A7 core 1 reset - - - - - y y y y y y y y y - - -
Cortex-A7 core 2 reset - - - - - x x x x x x x x x - - -
Cortex-A7 core 3 reset - - - - - w w w w w w w w w - - -
Cortex-A7 core 0 PORESET - - - - - - z z - - - z z z - - -
Cortex-A7 core 1 PORESET - - - - - - y y - - - y y y - - -
Cortex-A7 core 2 PORESET - - - - - - x x - - - x x x - - -
Cortex-A7 core 3 PORESET - - - - - - w w - - - w w w - - -
Cortex-A7 cluster reset - - - - - - - - - - - - - - - - -
System - - - - - - - - - - - - - - - - -
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