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System Static Configuration Read Register, DCS_CFG_R

The DCS_CFG_R register discovers the values that were applied to system static configuration input pins when the system was powered on, that is, system power-on reset.

The following table shows the bit assignments.

Table 3-35 DCS_CFG_R Register bit assignments

Bits Name Type Description
[31:28] NUM_CPU3 RO Reserved for the NUM_CPU configuration for cluster 3. This system does not contain a cluster 3 and this field is RAZ.
[27:24] NUM_CPU2 RO Reserved for the NUM_CPU configuration for cluster 2. This system does not contain a cluster 2 and this field is RAZ.
[23:20] NUM_CPU1 RO

Returns the NUM_CPU configuration for Cluster 1, Cortex®‑A7 cluster:

0x0 Cluster not present.
0x1 One core cluster.
0x2 Two core clusters.
... And so on.
[19:16] NUM_CPU0 RO

Returns the NUM_CPU configuration for Cluster 0, Cortex‑A15 cluster:

0x0 Cluster not present.
0x1 One core cluster.
0x2 Two core clusters.
... And so on.
[15:2] - RAZ Reserved.
[1:0] CFG_ACTIVECLUSTER RO Returns the value that was driven on the CFG_ACTIVECLUSTER configuration inputs at the last system power-on reset.
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