Table 1.3 shows the AHB interface signals used when the ARM922T is acting as the bus master.
Address output bus
The 32-bit system address bus.
These signals indicate the type of burst transfer:
001 = INCR burst
011 = INCR4 burst
101 = INCR8 burst.
When the processor requires the use of the bus, this is HIGH.
When the processor is the granted bus master, this signal is HIGH. Ownership of the address/control signals changes at the end of a transfer when HREADYM is HIGH, so a bus master gains access to the bus when both HREADYM and HGRANTM are HIGH.
When the processor is the bus master and requires locked access to the bus, this signal is HIGH.
These signals provide information about the current memory access:
HPROTM is 0 if the transfer is an opcode fetch, or 1 for a data access
HPROTM is 0 if the transfer is a User access, or 1 for a Privileged access
HPROTM is 1 if the transfer is bufferable, or 0 if it is not
HPROTM is 1 if the transfer is cachable, or 0 if it is not.
Read data bus
The 32-bit data input bus.
This signal is driven HIGH by the selected slave to indicate that a bus transfer has finished. It is driven LOW to extend a bus transfer.
These signals provide additional information on the status of a transfer:
00 = OKAY
01 = ERROR
10 = RETRY
11 = SPLIT.
These signals indicate the size of the transfer:
000 = a byte (8?bit)
001 = half-word (16-bit)
010 = word (32-bit)
These signals indicate the type of the current transfer:
00 = IDLE
01 = BUSY
10 = NONSEQUENTIAL
11 = SEQUENTIAL.
Write data bus
The 32-bit data output bus.
During a write operation, this signal is HIGH. It is LOW during a read operation.
Table 1.4 shows the AHB interface signals used when the ARM922T is acting as the bus master or as the bus slave.
This clock controls all bus transfers. All signal timings are related to the rising edge of this signal.
Put this signal LOW to reset the system and the bus. It can be asserted asynchronously, but must be de-asserted synchronously. HRESETn must be held LOW for a minimum of five clock cycles. To completely reset the system, nTRST must also be placed LOW.
Table 1.5 shows the AHB interface signals used when the ARM922T is acting as the bus slave.
Address input bus
The address input bus used when the processor is a bus slave.
Read data bus
The 32-bit data output bus used to transfer data from the processor to the bus master during read operations.
When a transfer is complete, this signal is HIGH. This signal can be driven LOW to extend a transfer.
When this signal is HIGH, it indicates that a transfer between the bus master (TIC, when the ARM922T is in test mode) and another slave has finished. The signal is driven LOW to extend a bus transfer. If both master and slave ports are connected to the same AHB, then this signal must be connected to HREADYM.
The transfer response provides additional information on the status of a transfer. This will always indicate:
00 = OKAY
When the current transfer is intended for the processor, this signal must be placed HIGH. The signal is a combinatorial decode of the address bus. Each AHB slave has its own select signal.
This signal indicates that a transfer is occurring:
0 = IDLE/BUSY
1 = SEQUENTIAL/NONSEQUENTIAL.
Write data bus
The 32-bit data input bus data used to transfer data from the bus master to the processor.
This signal indicates a write transfer when it is HIGH and a read transfer when it is LOW.
Table 1.6 shows the coprocessor interface signals.
Coprocessor handshake decode
The handshake signals from the Decode stage of the coprocessor pipeline follower.
Coprocessor handshake execute
The handshake signals from the Execute stage of the coprocessor pipeline follower.
This clock controls the operation of the coprocessor interface.
Coprocessor data out
The 32-bit data bus for transfers from the processor to the coprocessor.
Coprocessor data in
The 32-bit data bus for transfers from the coprocessor to the processor.
Coprocessor data out enable
When tied LOW, the CPID and CPDOUT buses are held stable.
When tied HIGH, the CPID and CPDOUT buses are enabled.
Normally this is a static configuration signal.
Coprocessor data in
The 32-bit instruction data bus for transferring instructions to the pipeline follower in the coprocessor.
Coprocessor late cancel
When this signal is HIGH during the first Memory cycle, the coprocessor must cancel the instruction without updating the coprocessor state.
When there is a coprocessor instruction in the Execute stage of the pipeline, and it must be executed, this signal is HIGH.
Coprocessor Thumb bit
When the coprocessor interface is in Thumb state, this signal is HIGH.
Not coprocessor memory request
When the coprocessor should read an instruction from CPID[31:0], this signal is LOW.
Not coprocessor translate
When the coprocessor interface is in a privileged mode, this signal is LOW.
Not coprocessor wait
When cycles must be extended on the coprocessor interface, this signal is LOW.
Table 1.7 shows the JTAG and TAP controller signals.
Test access port identification
Static configuration signals to determine the device identification (ID) code:
Bits 31:28 are for the revision code
Bits 27:12 are for the product code
Bits 11:1 are the manufacturer’s ID code
Bit 0 must be 1 (IEEE specified).
The clock for JTAG signals.
Test data input
JTAG serial input.
Test data output
JTAG serial output.
Not TDO enable
When serial data is being driven out on the TDO output, this is HIGH. This signal is normally used as an output enable for a TDO pin in a packaged part.
Test mode select
This signal selects the next state, from the two possible options, for every state transition of the JTAG state machine used in the TAP controller.
Not test reset
To correctly reset the boundary scan logic, this signal must be pulsed or driven LOW. This signal must be driven LOW whenever HRESETn is used to reset the processor to ensure correct processor operation.
Table 1.8 shows the debug signals.
Communications channel receive
When the communications channel receive buffer contains data waiting to be read by the processor, this signal is HIGH.
Communications channel transmit
When the communications channel transmit buffer is empty, this signal is HIGH.
When the processor is in debug state, this signal is HIGH.
A static configuration signal that disables the debug features when LOW.
Internal debug request
This is a logical OR of EDBGRQ and bit 1 of the debug control register.
This signal provides an input for external data watchpoints to be implemented. External watchpoints can be used to let hardware force the processor into debug state.
External clock output
For use by external devices. This is a copy of the clock used by the processor, as modified by clock switching, or debug state.
External debug request
Place this HIGH to request that the processor enter debug state when execution of the current instruction has completed.
External input 0
This is connected to watchpoint unit 0 of the EmbeddedICE logic in the processor, and permits breakpoints or watchpoints to be dependent on an external condition.
External input 1
This is connected to watchpoint unit 1 of the EmbeddedICE logic in the processor, and permits breakpoints or watchpoints to be dependent on an external condition.
This signal provides an input for external instruction breakpoints to be implemented. External breakpoints can be used to let hardware force the processor into debug state.
When the instruction in the Execute stage of the pipeline has been executed, this signal goes HIGH.
EmbeddedICE rangeout 0
When the EmbeddedICE watchpoint unit 0 has matched the conditions currently present on the address, data, and control buses, this signal is HIGH. This signal is independent of the state of the watchpoint unit enable control bit.
EmbeddedICE rangeout 1
When the EmbeddedICE watchpoint unit 1 has matched the conditions currently present on the address, data, and control buses, this signal is HIGH. This signal is independent of the state of the watchpoint unit enable control bit.
Enable TrackingICE mode
Place this HIGH to enable TrackingICE mode for debugging purposes.
Table 1.9 shows the INTEST/EXTEST wrapper signals.
Scan data input
Scan data input to the start of the INTEST/EXTEST wrapper.
Scan data output
Scan data output from the end of the INTEST/EXTEST wrapper.
Test scan inputs
Test scan inputs to each subsection of the wrapper.
Test scan outputs
Test scan outputs from each subsection of the wrapper.
Enables scanning of data through the INTEST/EXTEST wrapper.
This signal is HIGH during an INTEST operation.
This signal is HIGH during an EXEST operation.
Table 1.10 shows the miscellaneous signals.
When operating in big-endian configuration, this signal is HIGH. LOW for little-endian.
Buffered version of FCLK input.
Used when the processor is in the synchronous or asynchronous clocking mode (not during fast bus mode).
Determines the state of the V bit in Register 1 of CP15 coming out of reset. When HIGH, V bit is 1 coming out of reset. When LOW, V-Bit is 0 coming out of reset.
Set this HIGH if interrupts are synchronous to the processor clock. LOW for asynchronous interrupts.
Not fast interrupt request
Place this signal LOW to generate a fast interrupt request.
Not interrupt request
Place this LOW to generate an interrupt request.
Scan data in to the AHB wrapper.
Scan data out from the AHB wrapper.
Table 1.11 shows the ETM interface signals.
These signals connect directly to the equivalent signals on the ETM9.
This signal connects directly to the equivalent signal on the ETM9. It must be tied LOW if no ETM is connected.