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1.5. Interfaces on the ARM922T with AHB SoC

Table 1.3 shows the AHB interface signals used when the ARM922T is acting as the bus master.

AHB interface signals used when ARM922T is the bus master
NameDirectionDescription

HADDRM[31:0]

Address output bus

Output

The 32-bit system address bus.

HBURSTM[2:0]

Burst type

Output

These signals indicate the type of burst transfer:

001 = INCR burst

011 = INCR4 burst

101 = INCR8 burst.

HBUSREQM

Bus request

Output

When the processor requires the use of the bus, this is HIGH.

HGRANTM

Bus grant

Input

When the processor is the granted bus master, this signal is HIGH. Ownership of the address/control signals changes at the end of a transfer when HREADYM is HIGH, so a bus master gains access to the bus when both HREADYM and HGRANTM are HIGH.

HLOCKM

Locked transfers

Output

When the processor is the bus master and requires locked access to the bus, this signal is HIGH.

HPROTM[3:0]

Protection control

Output

These signals provide information about the current memory access:

HPROTM[0] is 0 if the transfer is an opcode fetch, or 1 for a data access

HPROTM[1] is 0 if the transfer is a User access, or 1 for a Privileged access

HPROTM[2] is 1 if the transfer is bufferable, or 0 if it is not

HPROTM[3] is 1 if the transfer is cachable, or 0 if it is not.

HRDATAM[31:0]

Read data bus

Input

The 32-bit data input bus.

HREADYM

Transfer done

Input

This signal is driven HIGH by the selected slave to indicate that a bus transfer has finished. It is driven LOW to extend a bus transfer.

HRESPM[1:0]

Transfer response

Input

These signals provide additional information on the status of a transfer:

00 = OKAY

01 = ERROR

10 = RETRY

11 = SPLIT.

HSIZEM[2:0]

Transfer size

Output

These signals indicate the size of the transfer:

000 = a byte (8?bit)

001 = half-word (16-bit)

010 = word (32-bit)

HTRANSM[1:0]

Transfer type

Output

These signals indicate the type of the current transfer:

00 = IDLE

01 = BUSY

10 = NONSEQUENTIAL

11 = SEQUENTIAL.

HWDATAM[31:0]

Write data bus

Output

The 32-bit data output bus.

HWRITEM

Transfer direction

Output

During a write operation, this signal is HIGH. It is LOW during a read operation.

Table 1.4 shows the AHB interface signals used when the ARM922T is acting as the bus master or as the bus slave.

AHB interface signals used when ARM922T is the bus master or a bus slave
NameDirectionDescription

HCLK

Bus clock

Input

This clock controls all bus transfers. All signal timings are related to the rising edge of this signal.

HRESETn

Reset

Input

Put this signal LOW to reset the system and the bus. It can be asserted asynchronously, but must be de-asserted synchronously. HRESETn must be held LOW for a minimum of five clock cycles. To completely reset the system, nTRST must also be placed LOW.

Table 1.5 shows the AHB interface signals used when the ARM922T is acting as the bus slave.

AHB interface signals used when ARM922T is a bus slave
NameDirectionDescription

HADDRS[11:2]

Address input bus

Input

The address input bus used when the processor is a bus slave.

HRDATAS[31:0]

Read data bus

Output

The 32-bit data output bus used to transfer data from the processor to the bus master during read operations.

HREADYOUTS

Transfer done

Output

When a transfer is complete, this signal is HIGH. This signal can be driven LOW to extend a transfer.

HREADYS

Transfer done

Input

When this signal is HIGH, it indicates that a transfer between the bus master (TIC, when the ARM922T is in test mode) and another slave has finished. The signal is driven LOW to extend a bus transfer. If both master and slave ports are connected to the same AHB, then this signal must be connected to HREADYM.

HRESPS[1:0]

Transfer response

Output

The transfer response provides additional information on the status of a transfer. This will always indicate:

00 = OKAY

HSELS

Slave select

Input

When the current transfer is intended for the processor, this signal must be placed HIGH. The signal is a combinatorial decode of the address bus. Each AHB slave has its own select signal.

HTRANS1S

Transfer

Input

This signal indicates that a transfer is occurring:

0 = IDLE/BUSY

1 = SEQUENTIAL/NONSEQUENTIAL.

HWDATAS[31:0]

Write data bus

Input

The 32-bit data input bus data used to transfer data from the bus master to the processor.

HWRITES

Transfer direction

Input

This signal indicates a write transfer when it is HIGH and a read transfer when it is LOW.

Table 1.6 shows the coprocessor interface signals.

Coprocessor interface signals
NameDirectionDescription

CHSDE[1:0]

Coprocessor handshake decode

Input

The handshake signals from the Decode stage of the coprocessor pipeline follower.

CHSEX[1:0]

Coprocessor handshake execute

Input

The handshake signals from the Execute stage of the coprocessor pipeline follower.

CPCLK

Coprocessor clock

Output

This clock controls the operation of the coprocessor interface.

CPDOUT[31:0]

Coprocessor data out

Output

The 32-bit data bus for transfers from the processor to the coprocessor.

CPDIN[31:0]

Coprocessor data in

Input

The 32-bit data bus for transfers from the coprocessor to the processor.

CPEN

Coprocessor data out enable

Input

When tied LOW, the CPID and CPDOUT buses are held stable.

When tied HIGH, the CPID and CPDOUT buses are enabled.

Normally this is a static configuration signal.

CPID[31:0]

Coprocessor data in

Input

The 32-bit instruction data bus for transferring instructions to the pipeline follower in the coprocessor.

CPLATECANCEL

Coprocessor late cancel

Output

When this signal is HIGH during the first Memory cycle, the coprocessor must cancel the instruction without updating the coprocessor state.

CPPASS

Coprocessor pass

Output

When there is a coprocessor instruction in the Execute stage of the pipeline, and it must be executed, this signal is HIGH.

CPTBIT

Coprocessor Thumb bit

Output

When the coprocessor interface is in Thumb state, this signal is HIGH.

nCPMREQ

Not coprocessor memory request

Output

When the coprocessor should read an instruction from CPID[31:0], this signal is LOW.

nCPTRANS

Not coprocessor translate

Output

When the coprocessor interface is in a privileged mode, this signal is LOW.

nCPWAIT

Not coprocessor wait

Output

When cycles must be extended on the coprocessor interface, this signal is LOW.

Table 1.7 shows the JTAG and TAP controller signals.

JTAG and TAP controller signals
NameDirectionDescription

TAPID[31:0]

Test access port identification

Input

Static configuration signals to determine the device identification (ID) code:

Bits 31:28 are for the revision code

Bits 27:12 are for the product code

Bits 11:1 are the manufacturer’s ID code

Bit 0 must be 1 (IEEE specified).

TCK

Test clock

Input

The clock for JTAG signals.

TDI

Test data input

Input

JTAG serial input.

TDO

Test data output

Output

JTAG serial output.

nTDOEN

Not TDO enable

Output

When serial data is being driven out on the TDO output, this is HIGH. This signal is normally used as an output enable for a TDO pin in a packaged part.

TMS

Test mode select

Input

This signal selects the next state, from the two possible options, for every state transition of the JTAG state machine used in the TAP controller.

nTRST

Not test reset

Input

To correctly reset the boundary scan logic, this signal must be pulsed or driven LOW. This signal must be driven LOW whenever HRESETn is used to reset the processor to ensure correct processor operation.

Table 1.8 shows the debug signals.

Debug signals
NameDirectionDescription

COMMRX

Communications channel receive

Output

When the communications channel receive buffer contains data waiting to be read by the processor, this signal is HIGH.

COMMTX

Communications channel transmit

Output

When the communications channel transmit buffer is empty, this signal is HIGH.

DBGACK

Debug acknowledge

Output

When the processor is in debug state, this signal is HIGH.

DBGEN

Debug enable

Input

A static configuration signal that disables the debug features when LOW.

DBGRQI

Internal debug request

Output

This is a logical OR of EDBGRQ and bit 1 of the debug control register.

DEWPT

External watchpoint

Input

This signal provides an input for external data watchpoints to be implemented. External watchpoints can be used to let hardware force the processor into debug state.

ECLK

External clock output

Output

For use by external devices. This is a copy of the clock used by the processor, as modified by clock switching, or debug state.

EDBGRQ

External debug request

Input

Place this HIGH to request that the processor enter debug state when execution of the current instruction has completed.

EXTERN0

External input 0

Input

This is connected to watchpoint unit 0 of the EmbeddedICE logic in the processor, and permits breakpoints or watchpoints to be dependent on an external condition.

EXTERN1

External input 1

Input

This is connected to watchpoint unit 1 of the EmbeddedICE logic in the processor, and permits breakpoints or watchpoints to be dependent on an external condition.

IEBKPT

External breakpoint

Input

This signal provides an input for external instruction breakpoints to be implemented. External breakpoints can be used to let hardware force the processor into debug state.

INSTREXEC

Instruction executed

Output

When the instruction in the Execute stage of the pipeline has been executed, this signal goes HIGH.

RANGEOUT0

EmbeddedICE rangeout 0

Output

When the EmbeddedICE watchpoint unit 0 has matched the conditions currently present on the address, data, and control buses, this signal is HIGH. This signal is independent of the state of the watchpoint unit enable control bit.

RANGEOUT1

EmbeddedICE rangeout 1

Output

When the EmbeddedICE watchpoint unit 1 has matched the conditions currently present on the address, data, and control buses, this signal is HIGH. This signal is independent of the state of the watchpoint unit enable control bit.

TRACK

Enable TrackingICE mode

Input

Place this HIGH to enable TrackingICE mode for debugging purposes.

Table 1.9 shows the INTEST/EXTEST wrapper signals.

INTEST/EXTEST wrapper signals
NameDirectionDescription

WP_SI

Scan data input

Input

Scan data input to the start of the INTEST/EXTEST wrapper.

WP_SO

Scan data output

Output

Scan data output from the end of the INTEST/EXTEST wrapper.

WP_SI_INT[7:1]

Test scan inputs

Input

Test scan inputs to each subsection of the wrapper.

WP_SO_INT[6:0]

Test scan outputs

Output

Test scan outputs from each subsection of the wrapper.

SCANEN

Scan enable

Input

Enables scanning of data through the INTEST/EXTEST wrapper.

INTEST

Input

This signal is HIGH during an INTEST operation.

EXTEST

Input

This signal is HIGH during an EXEST operation.

Table 1.10 shows the miscellaneous signals.

Miscellaneous signals
NameDirectionDescription

BIGENDOUT

Big-endian output

Output

When operating in big-endian configuration, this signal is HIGH. LOW for little-endian.

FCLKOUT

Buffered FCLK

Output

Buffered version of FCLK input.

FCLK

Fast clock

Input

Used when the processor is in the synchronous or asynchronous clocking mode (not during fast bus mode).

VINITHI

Vectors high

Input

Determines the state of the V bit in Register 1 of CP15 coming out of reset. When HIGH, V bit is 1 coming out of reset. When LOW, V-Bit is 0 coming out of reset.

ISYNC

Synchronous interrupts

Input

Set this HIGH if interrupts are synchronous to the processor clock. LOW for asynchronous interrupts.

nFIQ

Not fast interrupt request

Input

Place this signal LOW to generate a fast interrupt request.

nIRQ

Not interrupt request

Input

Place this LOW to generate an interrupt request.

SI

Scan in

Input

Scan data in to the AHB wrapper.

SO

Scan out

Output

Scan data out from the AHB wrapper.

Table 1.11 shows the ETM interface signals.

ETM interface signals
NameDirectionDescription

ETMBIGEND

ETMCHSD[1:0]

ETMCHSE[1:0]

ETMCLOCK

ETMDA[31:0]

ETMDABORT

ETMDBGACK

ETMDD[31:0]

ETMDMAS[1:0]

ETMDMORE

ETMDnMREQ

ETMDnRW

ETMDSEQ

ETMHIVECS

ETMIA[31:1]

ETMIABORT

ETMID15To8[15:8]

ETMID31To24[31:24]

ETMInMREQ

ETMINSTREXEC

ETMISEQ

ETMITBIT

ETMLATECANCEL

ETMPASS

ETMRNGOUT[1:0]

ETMnWAIT

Output

These signals connect directly to the equivalent signals on the ETM9.

ETMPWRDOWN

Input

This signal connects directly to the equivalent signal on the ETM9. It must be tied LOW if no ETM is connected.

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