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Glossary

The items in this glossary are listed in alphabetical order, with any symbols and numerics appearing at the end.

ACP

Accelerator Coherency Port. See Accelerator Coherency Port.

AHB

Advanced Hardware Bus. The main system bus interface in the AMBA2 specification.

AMBA

Advanced Microcontroller Bus Architecture.

AMP

See Asymmetric Multi-Processing.

APB

Advanced Peripheral Bus. The simple peripheral bus interface in the AMBA2 and AMBA3 specifications.

Asset

A resource of value which needs protecting in a secure system.

Asymmetric Multi-Processing

Execution within a multi-processor cluster without utilizing hardware enforced data coherency.

Attack

The act of trying to acquire, damage or disrupt an asset.

Attacker

A person creating or performing an attack.

Authenticity

Authentic data is data which can be shown to be in a trusted state.

AXI

Advanced eXtensible Interface. The main SoC level system bus interface in the AMBA3 specification.

Class-break

A single attack that can be used to break a significant number of similar devices.

CODEC

enCOder / DECoder algorithms used for compressing and decompressing data. Typically used for audio and video media files.

Confidentiality

An asset that is confidential cannot be copied or stolen by an attacker.

CP15

The ARM processor system control coprocessor.

Defend

The act of protecting an asset against an attack.

DRM

Digital Rights Management.

GIC

Generic Interrupt Controller. See PrimeCell Generic Interrupt Controller - PL390.

Hack attack

An attack which is performed using software-only methods.

Hacker

See Attacker.

Integrity

An asset which has integrity cannot be modified.

IP

Intellectual Property.

Lab attack

An attack that is capable of observing and altering all aspects or a device.

Monitor mode

A new processor mode added as part of the Security Extensions to facilitate the context switching between the two virtual processors.

Monitor, the

The implementation defined software that runs in Monitor mode to context switch between the two virtual processors.

Non-secure

(1) A device (master or slave) that exists in an untrusted part of the system.

(2) The untrusted virtual processor in an ARM processor implementing the Security Extensions.

(3) A transaction on the bus trying to access a Non-secure device.

Normal world

The system environment that encompasses all Non-secure devices and software.

One-Time- Programmable memory

A memory device that can only be programmed once, but which allows per-device customization. Typically implemented using fuse technology, such as poly-silicon fuse or metal layer fuse.

OTP memory

See One-Time-Programmable memory.

SCU

See Snoop Control Unit.

Secure

(1) A device (master or slave) that exists in the trusted part of the system.

(2) The trusted virtual processor in an ARM processor implementing the Security Extensions.

(3) A transaction on the bus trying to access a Secure device. Only Secure masters can create Secure bus transactions.

Secure world

The system environment that encompasses all Secure devices and software. Some Secure devices may allow access to Non-secure devices to be performed, for example, an ARM processor using World-shared memory.

Secure Monitor Call

An ARM instruction added to the ARM cores implementing the Security Extensions. This instruction allows privileged code in the Normal world and the Secure world to switch the processor into monitor mode.

Security Extensions

The extensions made to the ARM processor cores to enable the TrustZone technology. This primarily encompasses the creation of two virtual processors within a single physical processor core.

Shack attack

An attack performed with simple hardware, such as logic analyzers, but which cannot access resources within a integrated circuit package.

SMP

See Symmetric Multi-Processing.

Snoop Control Unit

Part of a multi-processor cluster which maintains data coherency between the data caches of processor executing in Symmetric Multi-Processing mode.

SoC

See System-on-a-Chip.

Symmetric Multi-Processing

Execution within a multi-processor cluster utilizing hardware enforced coherency of the L1 data cache.

System-on-a-Chip

An integrated device containing the majority of a device’s logic, including processors, memory controllers, and peripherals.

TCM

See Tightly Coupled Memory.

Tightly Coupled Memory

Fast SRAM located at the same level of the memory hierarchy as the level one cache.

TrustZone

The security technology from ARM that enables the construction of a Normal world and a Secure world.

TZASC

TrustZone Address Space Controller. See PrimeCell TrustZone Address Space Controller - PL380.

TZMA
TZPC
World-shared memory

Non-secure memory mapped into the Secure world using the MMU of the ARM processor.

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