The ARM architecture includes support for multiprocessor designs with between one and four processors in a cluster. The processors in the cluster can be configured to execute either in Symmetric Multi-Processing (SMP) mode, or in Asymmetric Multi-Processing (AMP) mode.
When a processor is executing in SMP mode the cluster’s Snoop Control Unit (SCU) will transparently keep data which is shared across the SMP processors coherent in the L1 data cache. When a processor is executing in AMP mode the executing software must manually maintain memory coherency if it is needed.
These multiprocessor systems may implement the ARM Security Extensions, giving each processor in the cluster the programmer’s model features described earlier in this chapter. The ARM processor which currently implements both the multiprocessor features and the security features is the Cortex-A9 MPCore processor
Multiprocessor systems often include an Accelerator Coherency Port which allows an external bus master to access the same physical memory view as the processor cluster. See Accelerator Coherency Port for further details.
Each of the processors within the multiprocessor cluster has a Normal world and a Secure world. This gives a four processor cluster a total of eight virtual processors, each with independent control over their MMU configuration.
Any number of the processors in the cluster may be in the Secure world at any point in time, and the processors can transition between the worlds independently of other processors in the cluster. A specific software implementation may choose to restrict the concurrent execution of Secure world software to reduce the security risks associated with complex software designs.
The potential impact of multiprocessing on Secure world software design is discussed in Secure software and multiprocessor systems.
As described in Caches, each of the cache lines in the cluster stores the security state of the data it contains as part of its tag. This enables the concurrent storage of Secure and Non-secure data within the L1 processor data caches when the processors within the cluster are executing in SMP mode. The coherency hardware uses the whole cache tag when performing coherency operations, allowing it to keep both Secure and Non-secure data coherent simultaneously.
The SCU includes a number of configuration registers which determine the configuration of the SCU itself, the configuration of each of the ARM processors in the cluster, and the accessibility of the processor-local timers to Non-secure memory transactions.
The SCU Access Control Register determines which processors in the cluster can reprogram the SCU’s configuration registers.
The SCU Secure Access Control Register determines if Non-secure accesses can reprogram the SCU configuration registers or access the processor-local timers.
The Cortex A-profile multiprocessor systems include an integrated interrupt controller based on the same technology as the PrimeCell Generic Interrupt Controller (PL390), described on PrimeCell Generic Interrupt Controller - PL390. This interrupt controller provides a flexible interrupt model which is capable of distributing prioritized interrupts across the multiprocessor cluster, interrupting lower priority interrupt handlers which are already executing if a higher priority interrupt is received.
In a multiprocessor system which also implements the Security Extensions this interrupt controller is TrustZone-aware. This allows it to manage Secure and Non-secure interrupts and prevent Non-secure memory accesses from reading or modifying the configuration of a Secure interrupt.
An interrupt managed by the integrated interrupt controller can be configured as a Secure interrupt by programming the appropriate bits in the Interrupt Security Register. Once and interrupt has been made Secure, no Non-secure access can modify its configuration.
All interrupts managed by the integrated interrupt controller are assigned a priority to determine whether they are allowed to interrupt an exception which is already being handled by the ARM processor. The hardware ensures that a lower priority interrupt will wait until a higher priority interrupt has been cleared before it issued to the processor. The priority space is partitioned to ensure that Secure interrupts can always be configured with a higher priority than the Non-secure interrupts. Assigning the Secure world a high priority interrupt can be used to prevent the Non-secure world performing a denial-of-service attack against the Secure world using interrupts.
The integrated interrupt controller can support the model described earlier in this chapter, causing Secure interrupts it controls to generate an FIQ exception and Non-secure interrupts it controls to generate an IRQ exception. In this case all interrupts are managed by the integrated interrupt controller, and no direct interrupt generation from an external interrupt controller is possible. The integrated interrupt controller can also support a number of legacy configurations which cause the FIQ and/or the IRQ exceptions to be generated by an external interrupt trigger, bypassing the integrated interrupt controller completely.
It is possible to independently configure the legacy interrupt generation for FIQ and IRQ exceptions.
If legacy mode is enabled only for FIQ exceptions then the integrated controller will route both Secure and Non-secure interrupts it controls to the IRQ exception vector.
If legacy mode is enabled only for IRQ exceptions then the integrated controller becomes unable to generate exceptions for Non-secure interrupts, and Secure interrupts will be routed to the FIQ exception vector.
If legacy mode is enabled for both FIQ and IRQ exceptions then the integrated interrupt controller is bypassed completely.
If they are used in a design, the legacy interrupt input signals to the processor cluster are typically generated by one or more external interrupt controllers. These external devices can be secured using the same methods as any other external AXI or APB slaves in a TrustZone system.
 Only a subset of the memory types supported by the MMU are kept coherent by the SCU. Refer to the appropriate processor Technical Reference Manual for details.