As processor clock frequencies rise it is increasingly desirable to include a level 2 cache between the core and the external memory system. This reduces the number of processor pipeline stalls experienced because of delays accessing external memory, enabling significantly faster performance in some applications, and typically reducing power consumption. Each of the caches in a TrustZone system needs to tag each cache line with the security state of the data that it contains, enabling concurrent storage of data from both worlds.
The ARM1176JZ(F)-S processor and the Cortex-A9 processors can make use of a separate level 2 cache controller, which must implement appropriate tagging of the security state. The ARM high performance PrimeCell Level 2 Cache Controller can be used for this purpose.
The Cortex-A8 processor includes an integrated L2 cache controller.