The interrupt model outlined in Secure interrupts, in which IRQ is configured as a Normal world interrupt and FIQ is configured as a Secure world interrupt, requires some core configuration by the monitor software on world switch.
The model proposes that if the processor is already executing in the correct world when an interrupt occurs, the hardware does not trap to monitor and jumps directly to the local world’s vector table. This avoids the overhead of a switch to the monitor and keeps the monitor software design simpler.
In a design that traps exceptions to the monitor you will trap to the appropriate entry in the monitor mode vector table; however the core will be in monitor mode, not the respective exception mode.
The Secure Configuration Register (SCR) in CP15 contains the settings which determine whether to trap IRQ, FIQ or external aborts to the monitor hardware. To implement the model proposed here the monitor needs to modify the content of the SCR on every world switch. When switching to the Normal world the SCR IRQ-bit must be cleared, and the SCR FIQ-bit must be set. When switching to the Secure world the SCR IRQ-bit must be set, and the SCR FIQ-bit must be cleared.
This is only one of many possible models for using interrupts in a TrustZone processor.