After deciding how the Secure world will make use of the SMP processor, a developer must then choose how to integrate any Secure interrupt sources in to the design.
In an architecture which executes the Secure world on a single fixed processor the interrupt routing is straightforward. The per-processor Interrupt Controller Processor Interface Control Register must be configured to suitably cause Secure interrupts to raise FIQ or IRQ exceptions, depending on how the software is designed to make use of the hardware features.
The interrupt routing model for an individual processor in a multi-processor system is described in more detail in the Interrupt model - monitor requirements. As that section shows, the monitor software for the processor which has to handle Secure or Non-secure interrupts needs to be able to route them to the appropriate world so that they can be handled by the correct exception handler.
In an SMP system where the Secure world is executing on a fixed single processor within the cluster, the FIQ interrupt can be made available for use by Non-secure interrupts on the processors not running the Secure world software. To prevent the hardware routing these interrupts to the Secure world the secure bootloader or the monitor software executing on these processors must ensure that the Secure Configuration Register in CP15 is appropriately programmed.
In a design where the Secure world only executes on a single processor it is usually necessary for the monitor software running on the other processors to reject Normal world attempts to switch world using the SMC instruction, interrupts, or external aborts.