If the choice is taken to implement a Secure world which is not capable of multi-processing then a design needs to be able to synchronize the communications between an SMP Normal world and the Secure world.
A design might choose to fix the Secure world execution on to one specific processor, which makes Secure interrupt routing simple, but also means that the Secure world may make the Normal world thread scheduling less efficient because it is using processor time which the Normal world cannot easily load balance. In this design the Normal world driver which communications with the Secure world usually needs to route requests to use the Secure world to the correct processor using inter-processor communications. In addition, the monitor software on the processors which the Secure world is not using must prevent the Normal world causing a malicious world switch. This architecture is shown in Figure 5.3, in which the Secure world software is only using CPU0.
An alternative design may choose to let the Secure world migrate around the multiple processors in the system, restricting it so that it is only executing on one processor at any single point in time. This makes the Secure world more efficient because it can run on the same processor as the Normal world application which is making use of it, and allows the Normal world to load balance its scheduling, but it makes the routing of the Secure interrupts to the necessary processor more complicated.