Release notes for the AArch32 Instruction Set Architecture for Arm A-profile Architecture
3 Oct 2022
This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.
The information relating to the 2022 Extensions of the A-profile Architecture is at Alpha quality. Alpha quality means that most major features of the specification are described in this release, but some features and details might be missing.
The information relating to previously released content, including FEAT_PMUv3_EXT32, is at Beta quality. Beta quality means that all major features of the specification are described, but some details might be missing.
This release introduces the 2022 Extensions of the A-profile Architecture. Some 2022 Extension features listed in the Known Issues, are not yet available.
- In AArch32.WatchpointByteMatch() the CONSTRAINED UNPREDICTABLE checks for DBGBVR<n> are removed.
- The pseudocode functions AArch64.RestrictPrediction() and AArch32.RestrictPrediction() are updated to check if the target exception level is implemented.
Many simple clarifications and corrections are also present, but are too small to be listed here.
All issues identified in the below list will be fixed in a future release.
- This release does not include the 2022 Extension features FEAT_ABLE, FEAT_RASv2, FEAT_PMUv3_EDGE, FEAT_PMUv3_SS, FEAT_SEBEP, FEAT_EBEP, FEAT_SPEv1p4, FEAT_SPE_FDS, FEAT_TRBE_EXT, FEAT_ETEv1p3, FEAT_ITE.
- The setting of FPEXC.DEX to '0' for unallocated instructions executed when AArch32.ExecutingCP10or11Instr() is missing from pseudocode.
- The execution Pseudocode for the AArch32 LDC and STC instructions show possible traps to Hyp mode.
- There is a mismatch between the encoding for VMOVL and some other instructions and the conditions defined for the groups they appear in. The encoding is correct. The group conditions for affected instructions will be clarified.
Potential upcoming changes
The following changes will be made to the way that Pseudocode is presented:
- Field values will be clarified where there are multiple fieldsets in a register.
- The meaning of real type will be changed to be limited to rational numbers. The SQRT operations will be changed appropriately to use an alternate function.