Release notes for the AArch32 Instruction Set Architecture for Arm A-profile Architecture

19 Dec 2022

Product Status

This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.

The information relating to the 2022 Extensions of the A-profile Architecture is at Alpha quality. Alpha quality means that most major features of the specification are described in this release, but some features and details might be missing.

The information relating to the rest of the Architecture is at Beta quality. Beta quality means that all major features of the specification are described, but some details might be missing.

Change history

Some 2022 Extension features are not yet available.

The following changes are made to instruction descriptions:

  • Added FEAT_AES condition to Advanced SIMD AESMC and AESIMC instructions.
  • Stated where any CONSTRAINED UNPREDICTABLE behavior of alias instructions can be found.

The following changes are made to the Shared Pseudocode:

  • Pseudocode changes are made to allow a PE to implement FEAT_RME without Secure state.
  • The functions AArch64.PhysicalSErrorSyndrome() and AArch32.PhysicalSErrorSyndrome() are updated to capture the EA syndrome field.

Many simple clarifications and corrections are also present, but are too small to be listed here. Some minor formatting changes are suppressed and not highlighted in the diff output.

Known issues

All issues identified in the below list will be fixed in a future release.

  • There is a mismatch between the encoding for VMOVL and some other instructions and the conditions defined for the groups they appear in. The encoding is correct. The group conditions for affected instructions will be clarified.
  • Some architectural features have limited or no descriptions in Pseudocode and are not fully covered by the functional testing. Affected features are listed below:
    • Address translation, Instruction Cache, Data Cache System instructions.
    • Ordering of memory accesses.
    • Halting debug.
    • Self-hosted trace and external trace.
    • RAS architecture.
    • Statistical Profiling Extension.
    • Performance Monitors Extension.
    • Activity Monitors Extension.
    • Generic Interrupt Controller.
    • Multi-processing.