Release notes for the AArch32 Instruction Set Architecture for Arm A-profile Architecture
6 July 2023
This release covers multiple versions of the architecture. The content relating to different versions is given different quality ratings.
The information relating to FEAT_MEC, the 2022 Extensions of the A-profile Architecture (except for FEAT_GCS, FEAT_D128, and the Debug and PMU 2022 features), and the rest of the Architecture is at Beta quality. Beta quality means that all major features of the specification are described, but some details might be missing.
The information relating to FEAT_GCS, FEAT_D128, and the Debug and PMU 2022 features remains at Alpha quality. Alpha quality means that most major features of the specification are described in this release, but some features and details might be missing.
There are no notable changes to the AArch32 instruction descriptions or Shared pseudocode in this release.
Many simple clarifications and corrections are present, but are too small to be listed here. Some minor formatting changes are suppressed and not highlighted in the diff output.
All issues identified in the below list will be fixed in a future release.
- There is a mismatch between the encoding for VMOVL and some other instructions and the conditions defined for the groups they appear in. The encoding is correct. The group conditions for affected instructions will be clarified.
- The setting of FPEXC.DEX and FPEXC.TFV bits for an invalid FPSCR.Len and FPSCR.Stride, for an allocated CP10 or CP11 instruction is missing from pseudocode.
Some architectural features have limited or no descriptions in pseudocode and are not fully covered by
the functional testing. Affected features are listed below:
- Address translation, Instruction Cache, Data Cache System instructions.
- Ordering of memory accesses.
- Halting debug.
- Self-hosted trace and external trace.
- RAS architecture.
- Statistical Profiling Extension.
- Performance Monitors Extension.
- Activity Monitors Extension.
- Generic Interrupt Controller.