Cortex-M7

I have a function that generates an UsageFault exception for test: intUsageFault_Trigger_UnalignedAccess(void){ int r = 0; volatile unsigned int* p; /* Not word aligned address */ p = (unsigned int*)0x20000002; /* Load word from unaligned address raises exception */ r = *p; return r;} When the program jumps to UsageFault_Handler(), I extract the SP and then I call a C routine to print some debug info - Pmd_Fault_Handler() voidUsageFault_Handler(void){ __asm__("TST LR, #4; "); __asm__("ITE EQ; "); __asm__("MRSEQ R0, MSP; "); __asm__("MRSNE R0, PSP; "); __asm__("MOV R1, LR; "); __asm__("b Pmd_Fault_Handler "); //...... __asm__("BX LR "); } voidPmd_Fault_Handler (uint32_t* pSP, int32_t exc){ regsss[0] = pSP[0]; regsss[1] = pSP[1]; regsss[2] = pSP[2]; regsss[3] = pSP[3]; regsss[4] = pSP[4]; regsss[5] = pSP[5]; regsss[6] = pSP[6]; regsss[7] = pSP[7]; ..... return; } PROBLEM: When returning from Pmd_Fault_Handler(), the program jump again to the beginning of this function instead of returning to UsageFault_Handler() The overall scope for me is to return from UsageFault_Handler() in a controlled manner and to continue execution from the next instruction from the caller of UsageFault_Trigger_UnalignedAccess(), but I cannot reach this - __asm__("BX LR "); - to be able to return from exception. Thanks!

Why is the ACELS interface of the R82 prohibited from non-modifiable bursts?

Is there a feasibility to support unsupervised AMP on A53 core having a dual cluster or quad cluster arch? Let us know some pointers around how to handle cache and MMU in case of AMP scenario.