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AArch64 MP
"PodWW Rfe PodRR Fre"
Cycle=Rfe PodRR Fre PodWW
Generator=diycross7 (version 7.54+01(dev))
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWW Rfe PodRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
P0 | P1 ;
MOV W0,#1 | LDR W0,[X1] ;
STR W0,[X1] | LDR W2,[X3] ;
MOV W2,#1 | ;
STR W2,[X3] | ;
exists
(1:X0=1 /\ 1:X2=0)
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(*
* The Armv8 Application Level Memory Model.
*
* This is a machine-readable, executable and formal artefact, which aims to be
* the latest stable version of the Armv8 memory model.
* If you have comments on the content of this file, please send an email to
* memory-model@arm.com
* For a textual version of the model, see section B2.3 of the Armv8 ARM:
* https://developer.arm.com/documentation/ddi0487/
*
* Authors:
* Will Deacon <will.deacon@arm.com>
* Jade Alglave <jade.alglave@arm.com>
* Nikos Nikoleris <nikos.nikoleris@arm.com>
* Artem Khyzha <artem.khyzha@arm.com>
*
* Copyright (C) 2016-present, Arm Ltd.
* All rights reserved.
*
Config:See documentation
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