Mali-G57 High Area Efficiency GPU

Arm Mali-G57 block diagram

About Mali-G57

The Arm Mali-G57 GPU is the first generation Valhall-based GPU for the mainstream market. Re-engineered to align with the Vulkan API, Mali-G57 brings higher-fidelity content to the mass market, from 4K/8K user interfaces in DTV to console-like graphics on smartphones. With 30% better performance density, 30% better energy efficiency for longer battery life, enhanced foveated rendering support for VR and up to 60% performance improvement for ML workloads, Mali-G57 pushes the boundaries on performance and efficiency for mainstream GPUs.

Contact us


Specifications

Features Value Description
Anti-Aliasing 4x MSAA
8x MSAA
16x MSAA
4x Multi-Sampling Anti-Aliasing (MSAA) with minimal performance drop.
API Support OpenGL® ES 1.1, 2.0, 3.1, 3.2
Vulkan 1.1
OpenCL™ 1.1, 1.2, 2.0 Full Profile
Renderscript
Full support for next-generation and legacy 2D/3D graphics applications.
Bus Interface AMBA®4 ACE, ACE-LITE and AXI Compatible with a wide range of bus interconnect and peripheral IP.
L2 Cache Configurable 64KB – 512KB
64KB-128KB for 1-Core.
128KB-256KB for 2-Core.
256KB for 3-Core.
1x256KB-2x256KB for 4-Core.
2x256KB-2x512KB for 5-Core and 6-Core configurations. 
Scalability 1 to 6 dual-pixel cores
Optimized for high area and energy efficiency to address mainstream device requirements.
Adaptive Scalable Texture Compression (ASTC) Low Dynamic Range (LDR) and High Dynamic Range (HDR).
Supports both 2D and 3D images.
ASTC offers several advantages over existing texture compression schemes by improving image quality, reducing memory bandwidth and thus energy use.
Arm Frame Buffer Compression (AFBC) Version 1.3
4x4 pixel block size
AFBC is a lossless image compression format that provides random access to pixel data to a 4x4 pixel block granularity. It is employed to reduce memory bandwidth both internally within the GPU and externally throughout the SoC.
Transaction Elimination 16x16 pixel block size Transaction Elimination spots the identical pixel blocks between two consecutive render targets and performs a partial update to the frame buffer with the changed pixel blocks only, which reduces memory bandwidth and thus energy.
Smart Composition  16x16 pixel block size Smart Composition extends the concept of Transaction Elimination to every stage of UI composition. Identical pixel blocks of input surfaces are not read, not processed for composition and not written to final frame buffer.
Foveated Rendering  3 levels of quality possible Foveated Rendering allows VR application to specify the shading rate to be used in each part of the screen. This helps the developer to reduce the workload of VR applications by selectively define the part of the screen that require less work from the GPU due to distortion introduced by the VR headset lenses.


Performance

Features Value Description
Frequency 850 MHz in 16nm
Throughput 1.7-10.2 Gpix/s in 16nm


  • A desktop, a folder, 3D shapes etc.
  • Development Tools for Graphics and Compute Applications

    A range of development tools to assist in the deployment of graphics applications and content on Mali GPU based systems.

    Learn more
  • A phone, a tablet, game console etc.
  • Mali Developer Center

    An online portal for a growing community of developers, technology partners, software vendors and content companies to create a thriving community around Mali embedded graphics IP.

    Learn more

Get Support

Community Blogs

Community Forums

Answered hardfault error
  • Cortex-M4
0 votes 898 views 4 replies Latest 2 days ago by 42Bastian Schick Answer this
Suggested answer Can I run an A9 program under A53 without any modification 0 votes 828 views 1 replies Latest 2 days ago by 42Bastian Schick Answer this
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) 0 votes 238 views 2 replies Latest 3 days ago by qinwenjian Answer this
Answered MPS2+ Expansion ports possible frequency and usage
  • ANSI
  • FPGA
  • iOS
  • Cortex-M
  • Cortex-M Prototyping System (V2M-MPS2)
0 votes 3503 views 6 replies Latest 3 days ago by kfzhang Answer this
Not answered There was a problem compiling the content above design start eval. 1 votes 80 views 0 replies Started 4 days ago by qinwenjian Answer this
Suggested answer Reading ETB from software
  • CoreSight ETB11
  • Cortex-A9
0 votes 2370 views 1 replies Latest 9 days ago by 42Bastian Schick Answer this
Answered hardfault error Latest 2 days ago by 42Bastian Schick 4 replies 898 views
Suggested answer Can I run an A9 program under A53 without any modification Latest 2 days ago by 42Bastian Schick 1 replies 828 views
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) Latest 3 days ago by qinwenjian 2 replies 238 views
Answered MPS2+ Expansion ports possible frequency and usage Latest 3 days ago by kfzhang 6 replies 3503 views
Not answered There was a problem compiling the content above design start eval. Started 4 days ago by qinwenjian 0 replies 80 views
Suggested answer Reading ETB from software Latest 9 days ago by 42Bastian Schick 1 replies 2370 views