Mali-V52 Video Processor

Mali-V52 Block Diagram.

About Mali-V52

Arm Mali-V52 is a video processor optimized for the mainstream market. Arm Mali-V52 provides significant area savings and uplifts in both encode quality and decode performance. Just one core of Mali-V52 can deliver 4K30FPS decode enabling premium 4K video in the smallest area. Arm Mali-V52 can simultaneously encode and decode using multiple codecs. Mali-V52 can achieve a total performance of up to 4K120 decode or 4K60 encode when configured with 4 cores.

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Key features

  • Area efficient multi-standard video encode and decode core. Configurable from 1-4 cores
  • Adds High 10 H.264 encode and decode capability to Levels 5.0 and 5.1 respectively
  • Adds AVS Part 2 (Jizhun) and Part 15 (AVS+, Guangdian) decode capability for YUV420

Key benefits

  • 2x decode performance
  • 38% smaller area
  • 15% encode quality improvement 

Specification

 Features Value
Description
Codec Support
For encode and decode : VP9 Profile 2 (10-bit) and Profile 0 (8-bit), HEVC Main 10 and Main, H.264 Hi10P/HP/MP/BP, VP8, JPEG. Decode only : MPEG4, MPEG2, VC-1/WMV, Real, H.263, AVS+/AVS
Driver and video streaming infrastructure based on OpenMAX™, which runs on the host CPU. 
Bus Interface
AMBA4 AXI Compatible with a wide range of bus interconnect and peripheral IP.
Memory System
MMU Built-in Memory Management Unit (MMU) to support virtual memory.
Performance 1080p60 to 4K120 Scalable from one to four cores with multiple performance points.

  • A mali gpu chip.
  • Arm Mali GPUS

    Including both graphics and GPU compute technology, Mali GPUs offer a diverse selection of scalable solutions for low power to high performance smartphones, tablets and DTVs.

    Learn more
  • Arm Mali DPUs

    The Mali Display Processors bring composition, scaling, rotation and image post-processing tasks from the GPU on to a dedicated processor to maximize device battery life.

    Learn more

Get Support

Arm Support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Mali-V52 Video Processor into their design. 

Arm training courses Open a support case
Answered Where do I find presentations and photos from SC'18? 1 votes 894 views 0 replies Started 5 months ago by John Linford Answer this
Not answered what action will be performed by the master based on the read and write responce in axi 4?
  • AXI
  • AXI4
0 votes 20 views 0 replies Started 8 hours ago by Hem Patel Answer this
Not answered Object detection 0 votes 15 views 0 replies Started 8 hours ago by Martin Peniak Answer this
Suggested answer Cortex-A Support in MacOS
  • Cortex-A
  • GNU
0 votes 466 views 4 replies Latest 8 hours ago by Ron Aaron Answer this
Not answered Trigger a Software Interrupt 0 votes 14 views 0 replies Started 9 hours ago by Aquox Answer this
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
  • R15 (PC Program Counter)
  • Cortex-M1
  • R13 (SP Stack Pointer)
  • Keil
0 votes 111 views 3 replies Latest 13 hours ago by 42Bastian Schick Answer this
Not answered Non-linearity sharing in deep neural networks (a flaw?) 0 votes 19 views 0 replies Started 14 hours ago by SeanCS Answer this
Not answered Create standalone function to be loaded into Code memory 0 votes 26 views 0 replies Started yesterday by RSB Answer this
Answered Load an image in QVGA format into a ARM Compute Library ICTensor.
  • Arm Compute Library (ACL)
0 votes 429 views 1 replies Latest 2 days ago by Gian Marco Iodice Answer this
Suggested answer Code is not run after loading into chip 0 votes 76 views 1 replies Latest 2 days ago by Bojan Potocnik Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 45 views 0 replies Started 2 days ago by jing Answer this
Answered Binary Semaphore upset by FIQ
  • Cortex-A
0 votes 877 views 20 replies Latest 5 days ago by 42Bastian Schick Answer this
Answered Where do I find presentations and photos from SC'18? Started 5 months ago by John Linford 0 replies 894 views
Not answered what action will be performed by the master based on the read and write responce in axi 4? Started 8 hours ago by Hem Patel 0 replies 20 views
Not answered Object detection Started 8 hours ago by Martin Peniak 0 replies 15 views
Suggested answer Cortex-A Support in MacOS Latest 8 hours ago by Ron Aaron 4 replies 466 views
Not answered Trigger a Software Interrupt Started 9 hours ago by Aquox 0 replies 14 views
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 13 hours ago by 42Bastian Schick 3 replies 111 views
Not answered Non-linearity sharing in deep neural networks (a flaw?) Started 14 hours ago by SeanCS 0 replies 19 views
Not answered Create standalone function to be loaded into Code memory Started yesterday by RSB 0 replies 26 views
Answered Load an image in QVGA format into a ARM Compute Library ICTensor. Latest 2 days ago by Gian Marco Iodice 1 replies 429 views
Suggested answer Code is not run after loading into chip Latest 2 days ago by Bojan Potocnik 1 replies 76 views
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 2 days ago by jing 0 replies 45 views
Answered Binary Semaphore upset by FIQ Latest 5 days ago by 42Bastian Schick 20 replies 877 views