Click the following links to find answers to frequently asked questions about Physical IP.

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General FAQs

Q: What documentation does Arm provide for my Physical IP?

Memory Compiler

You can find the following documents in the <install_path>/doc directory of your compiler:

  • User Guide: Describes supported memory configurations, pins, features, physical implementation guidelines, and how to use the compiler in GUI or command-line mode to generate EDA views.
  • Power management app note: Describes how to transition the memory to or from low-power modes.
  • Test and repair app note: Describes the memory test and repair features.
  • EDA support app note: Describes how to use various memory views with different EDA tools.
  • Voltus app note: Describes how to use Memory Compiler views to create Power Grid View (PGV) models for power analysis.

Logic

  • User Guide: Describes supported cell architectures and cell families. The user guide describes the supporting library kits for various implementation stages. You can download this user guide in the *LD* bundle.
  • Databook: Describes the functional behavior and electrical characteristics of each cell family that is supported in a platform. You can find this document in the <install_path>/doc directory of your IP.

GPIO

  • Technical Reference Manual (TRM): Describes supported cell architectures, cell families, and their electrical characteristics. The TRM also describes physical implementation using Arm Artisan GPIO Products. You can find this document in the <install_path>/doc directory of your IP.
  • Databook: Describes the functional behavior and electrical characteristics of each cell family that is supported in a platform. You can find this document in the <install_path>/doc directory of your IP.

POP

POP User Guide: Describes the processor, POP implementation methodology, IR drop analysis, floorplan trials, and PPA details. To read the user guide, download the *PA*-DOC* bundle. You can then find the guide in the <install_path>/doc directory of your IP.

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Q: If I have download issues, who do I contact?

You can contact specific groups if you have the following issues:

  • The required IP is not visible on the interface.
  • The required IP version is not visible on the interface.
  • IP permission or access issue
  • Unable to download the IP
  • Other download interface issues

The following table shows the contact email addresses for the download interfaces:

Download interface Contact
Connect support-connect@arm.com
Athena pdg-ds-licensing@arm.com
PDH pdg-ds-licensing@arm.com

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Q: What if I am unable to generate views?

If you are unable to generate views, use the following flow diagram to help you find a solution:

Unable to generate views flow diagram

If you are using a ROM compiler:

Ensure that you have created a ROM code file (.rcf) and are pointing to it when generating a view. You can find more details about generating the ROM code file in the compiler user guide present in the <compiler_install_path>/doc directory.

If you are still unable to generate views, open a support case and provide the following details:

  • Compiler SAP code and the compiler revision
  • Instance configuration with the option information on which the issue exists
  • Your run command and the run log file

If you are using an SRAM, Register File, or MRAM compiler:

  1. Navigate to <compiler_install_path>/, to review the compiler README.txt file.
  2. Select the valid memory options.
  3. For timing-dependent views, ensure that you have completed one of the following:
    • Select at least one PVT corner in the Corners Pane in the GUI.
    • Use the -corners option in the command line.

If you are still unable to generate views, open a support case and provide the following details:

  • Compiler SAP code and the compiler revision
  • Instance configuration with the option information on which the issue exists
  • Your run command and the run log file

Q: What do I do if I experience errors in EDA view verification?

If you are experiencing errors in EDA view verification, use the following flow diagram to help you find a solution:

Errors in EDA view verification flow diagram

Navigate to the <product_install_path>/doc directory, and check the View Validation Report (vvr*.txt) file. This file contains simulator information used in Arm IP qualification.

Do the simulator and the simulator version in the VVR file match with your verification run?

  • No: Contact the foundry or EDA vendor to get a workaround.
  • Yes: Open a support case and provide the following details:
    • Product SAP code and the product revision
    • Your run command and the run log file
    • Waveform, if applicable
    • For memories, provide memory instance configuration with the option information on which the issue exists.

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Q: What do I do if I experience errors in physical verification (DRC, LVS, or ERC)?

If you are experiencing errors in physical verification (DRC, LVS, or ERC), use the following flow diagram to help you find a solution:

Errors in physical verification flow diagram

Navigate to the <product_install_path>/doc directory and check the Design Assurance Report (DAR*.xls) file. This file contains PDK, simulator, and switch information that is used in Arm IP qualification.

Do the tool versions in the DAR*.xls file match with your verification run?

  • No:
    • If your tool versions are newer than the tool versions used by Arm during IP qualification, contact the foundry to check if your errors can be waived.
    • If your tool versions are older than the tool versions used by Arm during IP qualification, contact your EDA vendor to understand why the errors occur in an older version.
  • Yes:
    • Navigate to the <product_install_path>/doc directory and check the DAR Waiver (DAR-WAIVER*.doc) file. This file describes known errors that are waived by Arm during IP qualification.
    • If you do not see a waiver for your error, open a support case and provide the following details:
      • Product SAP code and the product revision
      • Your run command and the run log file
      • Snippet of the error
      • For memories, provide memory instance configuration with the option information on which the issue exists.

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Q: Why is Memory Explorer not generating datatables?

  • If you are using multiple compilers, try to generate the datatables of a single compiler. Often, the switch options or settings are different between multiple compilers, resulting in errors.
  • If you are unable to generate datatables using a single compiler, review the README*.txt file that is in the <compiler_install_path>/ directory. Check the dependencies between the compiler options and VT Modes or Corners.
  • If you are still unable to generate the datatable, open a support case and provide the following details:
    • Compiler SAP code and the compiler revision with the MemExplorer version
    • Instance configuration with the option information on which the issue exists
    • Your run command and the run log file
    • Screenshot of the error
    • Any input file that you are providing to MemExplorer

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Q: What to do if I experience silicon yield issues or failures?

Open a support case with the following details:

  • Product SAP code and the product revision
  • Foundry and process node
  • Have you contacted the foundry about this failure? What was their response?
  • List all Arm Physical IP products being used on this chip. Include the version of each product. For Memory products, include the size (word x bits and mux value) and the number of instances for each size.
  • Which Arm Physical IP products do you have issues with?
  • If there are multiple memory instances on a chip, do all instances show the same failure signature or behavior? Is there a yield difference between different instances?
  • Describe the failure or failures in as much detail as possible.
  • Are these failures observed from the parts on one wafer? One wafer lot? Multiple lots? What is the yield?
  • Does parametric test data for this lot show that the wafers are within the process spec? If not, what is out of spec? Give details of the out-of-spec parameters.
  • Did the foundry run any split lots? Is there any dependence to process corners?
  • Is the failure voltage-dependent? What data do you have? Are shmoo plots available?
  • Is the failure temperature-dependent? What data do you have? Are shmoo plots available?
  • If you have noticed voltage or temperature dependency, have you tried writing at one voltage or temperature, and then reading at another for SRAM and RF? What are the results?
  • From this scenario, can you determine whether the failure is in write mode or read mode? (Ignore this question for ROM issues.)
  • If using Two-port Register File or Dual-Port SRAM memories, do you see simultaneous read/write access to the same address or to the same row in the same clock cycle in either the BIST or in the system?
  • Is the failure frequency-dependent?
  • Is the failure mechanism pattern-dependent? What data do you have? Describe the pattern.
  • Is the memory tested by BIST? Can the memory be accessed by external pins?
  • Is physical failure bit map available? Have you noted address locations failing at different voltages?
  • Describe how power is connected to the failed instance or instances. How does that compare to other instances?
  • How are these instances oriented on the chip? All in same orientation, or some orthogonal, or flipped 180-degrees? Is there a yield difference among different orientations?

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Q: If there are any updates to my licensed IP, will Arm contact me?

You will receive the following types of automated email notifications from Arm:

Release notifications

If you have downloaded any Arm Physical IP for a given foundry or process, you will receive bi-weekly email notifications regarding any update releases that occurred during the previous two weeks. 

Product alerts

If you have downloaded Arm Physical IP, you will receive Product Alert PDFs by email. You can also find Product Alert PDFs in our Product Download Hub. Product Alerts describe issues, impacts, and workarounds related to the IPs and are released to seek immediate attention of end users.

Errata

If you have downloaded Arm Physical IP, you will receive Errata PDFs by email. You can also find Errata PDFs in our Product Download Hub. Errata describe issues, impacts, and workarounds related to the IPs. Errata are released to ensure that end users are updated on known issues that might not require immediate attention.

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Q: What if I cannot find my issues here?

Contact support-physical@arm.com or open a support case and provide the following details:

  • Product SAP code and the product revision
  • Your run command and the run log file
  • For memories, provide memory instance configuration with the option information on which the issue exists.

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Usage reporting FAQ

Q: What is Usage Reporting?

Usage reporting is the reporting of LICENSEE products that contains Arm IP. This includes a set of basic product information that is defined in your agreement. 

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Q: Why do I need to report on usage?

In exchange for the product that was downloaded from Arm DesignStart, LICENSEE agrees to report on each LICENSEE products. This includes a set of product information as defined in the agreement.

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Q: How do I access the Arm DesignStart usage reporting portal?

The URL for Arm DesignStart usage reporting portal is https://usagereport.arm.com. You will login through your Arm Single Sign-On. If you don’t have an Arm user account yet, please sign up for DesignStart here.

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Q: I am a DesignStart reporter. How do I add/replace a coworker as a new reporter?

Please contact your account owner or DesignStart Licensing Team (PDG-DS-Licensing@arm.com) if there is a reporter role transition or you need to add a new user from your organization for usage reporting.

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Q: When reporting a new/existing product into the usage reporting system, which product status should I pick?

Product Status Definition 
In design Back end views of Arm IP have been downloaded and either evaluation work or chip design work have begun, but no tape out yet
MPW MPW / Shuttle Run tape out
In production Multi-Layer-Mask or full mask tape out in either prototype or production
End of Life Tape out products terminated or reached end of life
Cancelled In design products are cancelled without reaching tape out, or no longer exist (include details of reasons for product cancellation)

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Q: How do I submit a product for certification?

After creating and saving a new product, look for the “Certify” button at the upper right corner of the product detail page:

 

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Q: Why can’t I see the “Certify” button to submit a product for certification?

If you cannot see the “Certify” button next to the “Edit” button in the upper right corner of the product detail page, that means the product you just entered is not Certification Ready and is missing certain required information. Please click the “Edit” button to add all required information such as foundry part number and Arm IP to make it Certification Ready. The fields with an asterisk next to them will be all the required information.

If the product is still in design and you do not have a foundry part number, please wait until it has been taped out to submit for certification.

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Q: Why can't I edit my product information after it is submitted for certification?

Product information page will be automatically locked and not editable once submitted for certification. Please contact your account owner or DesignStart Licensing Team (PDG-DS-Licensing@arm.com) if you find a typo or need to make changes to a product that’s already been submitted for certification.

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Q: What is product revision and when should I create a revision?

Revision can be created for the following purposes:

  • Tape out type changes from MPW to Full Mask.
  • Tape out type stays the same, but revised tape out ends up with a new foundry part number.

When you create a revision, all existing product information will be pre-populated except for the following:

  • Product name.
  • Foundry part number.

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Q: How do I attach the IP Confirmation Form, Artiscan Report or other relevant files to my product?

If you already have the IP Confirmation Form and Artiscan Report in hand when you create a product, please upload them through the two upload buttons on the “Creating New Product” page:

 

If you don’t have those files at the moment, please go ahead and submit your product. Your account owner in the DesignStart Licensing Team will assist you with the generation of the files when they review your product certification.

Download the Artiscan tool here.

Other files

If you’d like to attach other relevant files to the product, after creating and saving the new product, on the product detail page, click “Files” on the left to upload file:



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Q: What are the reporting periods?

Product certification

You can add new products and submit for certification anytime throughout the quarter. For new tape outs, preferably right after the product has been taped out for more accurate data.

Usage reporting

January 1-31 Q4 report
April 1-30 Q1 report
July 1-31 Q2 report
October 1-31 Q3 report

We will suspend accounts that are delinquent in fulfilling usage report at the end of the reporting window. Once suspended, your download function in DesignStart will be taken away. Suspended accounts will still be able to submit usage reports for current and previous quarters at https://usagereport.arm.com. Once we have received missing usage reports, we will reactivate your account.

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Q: Why do I see an error when logging off?

 

This is a known error that we are correcting. Although the error is appearing, you can be assured that you have successfully logged out.

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Q: Which browsers are compatible with the new reporting system?

We recommend you use Google Chrome and Mozilla Firefox for the best performance of our new reporting system. We are looking to make IE compatible as well, but will come later.

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Q: What are the key things I will need to do in the new usage reporting system?

  • Products - to create new products, submit for certification
  • Usage Reports - to update and submit the quarterly usage report
  • Follow-Ups - if Arm has any questions about the products or reports you submitted, your account owner will reach out to you by sending you a follow-up that’s attached to a product or a usage report. You will be able to see a new item under Follow-Ups on your homepage. You will receive an email notifying about the follow-up as well.

For more training information, please click here for training materials.

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Q: Can I submit a “zero report” if I don’t have any products to report on, didn’t tape out any wafer or have any status change for existing products?

After you click New Usage Report, on the usage report screen, there will be a Nothing to Report button in the upper right corner. You can click Nothing to Report if:

  • You have no products or products are in design and remain in design.
  • You have tape out products but no wafer was purchased.
  • No product status change for any existing products.

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Q: Why am I unable to log in with my existing username and password?

Single Sign-On has been incorporated for all usage reporting users. This will require e-mail address verification and will require you to sign up if you have not done so before.

To complete, follow the steps below:

  1. Click on Sign up now.

     
  2. Input your corporate e-mail address and click Send verification code.

     
  3. Enter the verification code that was sent to your e-mail address and then click Verify code.

     
  4. Create and confirm a new password, then click Create.

     
  5. After verification, you will be able to input your login credentials and Sign In to usage reporting system.

      

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