Artisan Logic IP
Artisan Logic IP solutions are the ideal choice across mainstream and advanced, deep submicron SoC designs, delivering optimal performance, power and area results. The Artisan Standard Cell Libraries are available in a variety of different architectures complemented by add-on kits such as the Power Management Kit and ECO Kit. The Artisan product portfolio covers over 15 foundries and numerous process variants.
FinFET logic libraries
Ultra-high density and high performance logic families with carefully crafted cell architecture support ideal power grids ranging from low to high power density designs. The Artisan libraries utilize combinations of Vt and channel length devices to enable optimal PPA across market segments. Deliverables support the latest EDA tools and flows, including Liberty Variation Format (LVF) to accurately account for the variation inherent in FinFET processes. FinFETs provide strong performance across voltages, and the Artisan libraries support wide characterization ranges to enable further tuning for performance and power requirements. FinFET libraries are available from 16/14nm down to 7/5nm.
Bulk CMOS logic libraries
Artisan Logic IP for bulk CMOS processes extends from 250nm to 22nm. The selected architectures include ultra-high density, high density, and high performance; each can be used within blocks on the same SoC. The logic libraries of the mainstream nodes consist of footprint compatible cells at various Vts and channel lengths, all to enable the SoC designer to generate PPA needed across a wide range of applications. Standard EDA flows and advanced power management features are supported; modeling includes full state-dependent power characterization for accurate predictions of silicon results.
SOI logic libraries
Arm has a long history with SOI products, starting with partially depleted SOI (PDSOI). Fully depleted SOI (FDSOI) libraries are now part of the Artisan logic IP portfolio, enabling the same modeling and implementation for FDSOI logic blocks as is used for bulk CMOS technology. Along with multiple threshold and channel length devices, FDSOI enables dynamic biasing for fine-grain control of performance-power trade-offs.
Artisan logic libraries undergo rigorous design assurance and view validation checks. The analysis and validation are done on stand-alone cells and within standard EDA flows from synthesis through GDSII creation to ensure products of the highest quality. Integration tests are run by the library development teams, the POP IP implementation teams and Arm processor teams to ensure clean end-user designs. Silicon testing is performed across process corners, voltages and temperatures; test chip reports are available on request.