POP IP Core Hardening

Arm POP IP Technology

Arm POP IP is the world’s leading implementation solution for Arm microprocessor technology; it is the bridge between the processors and the resulting silicon. A highly optimized physical IP solution for the microprocessors, Arm POP IP delivers a proven high performance or high density implementation solution while lowering technical and project risk.

Neoverse N1

Arm Neoverse N1 POP IP targets high performance implementations in advanced node processes. The POP IP realizes the revolutionary compute performance offered by Neoverse N1 for cloud-to-edge, networking and infrastructure. The Neoverse N1 POP IP truly accelerates the transformation to a scalable cloud to edge infrastructure.

The POP IP package consists of logic IP as well as high performance fast cache instances (FCIs) designs to meet the efficiency demands of networking and infrastructure markets. The implementation included as part of the POP IP addresses challenges unique to advanced node processes, particularly designing an optimal power grid to address IR drop, part of a comprehensive RTL-GDS flow supporting major EDA vendors.

Cortex-A55

The Arm Cortex-A55 POP IP is a highly successful implementation solution for Arm Cortex-A55 CPU. Products based on Cortex-A55 processor include smart-phone/tablet, DTV and consumer electronics segments. Cortex-A55 POP is available on 28nm and advanced process nodes. POP IP enables customers to implement Cortex-A55 processors in multiple configurations leveraging Arm DynamIQ technology. Cortex-A55 can be implemented with Cortex-A75 or Cortex-A76 with DynamIQ in a big.LITTLE system, multiple Cortex-A55 CPUs can be used in a high-performance/low-power combination, or a single implementation of Cortex-A55 can enable a single or multi-core CPU. 

Arm POP IP supports multiple L1/L2 cache sizes as well as support for ECC. The fast cache instances in Cortex-A55 support a special ‘Light Sleep Mode’ in conjunction with the Cortex-A55 CPU. The POP IP package consists of Cortex-A optimized logic IP as well as high performance fast cache instances (FCIs), along with a comprehensive RTL-GDS flow supporting major EDA vendors.

Cortex-A76

Arm Cortex-A76 POP IP is a high performance implementation for Cortex-A76 on FinFET technologies. Targeted at the premium mobile market, it can help customers achieve 3+GHz performance in silicon while consuming very low power in a small area. Arm POP IP for Cortex-A76 supports ECC as well as multiple L1/L2 configurations.

Developed in conjunction with Cortex-A76 CPU architects, Cortex-A76 POP technology includes specially customized memories which tie the physical IP and RTL closely to deliver a highly optimized integrated solution. The POP IP package consists of Cortex-A optimized logic IP, high performance fast cache instances (FCIs), and specially customized memories along with a comprehensive RTL-GDS flow supporting major EDA vendors.