Cortex-A15

Specifications

Architecture	Armv7-A
Multicore	1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology. Compatible with CCI-400 for up to two clusters, CCI-504 for up to four clusters, and a large level 3 cache for optimal performance.
ISA Support	Armv7-A Thumb-2 TrustZone security technology Neon Advanced SIMD DSP & SIMD extensions VFPv4 Floating point Hardware virtualization support Large Physical Address Extensions (LPAE) Integer Divide Fused MAC Hypervisor debug instructions
Memory Management Unit (MMU)	Armv7 Memory Management Unit
Debug & Trace	CoreSight

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Characteristics

The Cortex-A15 features a highly out-of-order processing engine with a 15 stage pipeline. This enables it to meet the requirements of modern day mobile computing where it must meet two opposite targets; high responsiveness or frame rate for gaming and web surfing, alongside maximizing the battery life to deliver an untethered user experience.

In a single-core configuration, the Cortex-A15 processor can achieve greater performance than the Cortex-A9 processor in key functions. This makes the processor ideal for devices which have rich functionality or need to execute functions at high speeds.

In order for devices to meet both targets simultaneously, Arm has invented big.LITTLE technology. By offering a ‘right core for the right task’ solution, devices can benefit from impressive power savings. Arm’s big.LITTLE technology assigns background and light tasks to the “LITTLE” core and the primary larger tasks to the “big” core. Not only does this allow the larger core to operate more efficiently as it is not trying to continuously context switch to cover the light threads, the consumer benefits from greatly increased battery life alongside top-end performance that can be greater than an individual Cortex-A15 core.

The Cortex-A15 processor can be implemented in a single or multicore configuration and can be paired with the Cortex-A7 to enable big.LITTLE configurations. This means that the processor provides a range of solutions for different use cases.

Cortex-A15 Technical Reference Manual

For system designers, system integrators and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

Read here
Cortex-A Series Programmer's Guide for Armv7-A

Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

Get the guide
Development Tools for Cortex-A

Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

Development Tools

Cortex-A comparison table (Armv7-A)

Feature	Cortex-A5	Cortex-A7	Cortex-A9	Cortex-A15	Cortex-A17
Instruction set architecture and extensions	Armv7-A	Armv7-A LPAE Virtualization	Armv7-A	Armv7-A LPAE Virtualization	Armv7-A LPAE Virtualization
Pipeline	In order	In order	Out of order	Out of order	Out of order
Superscalar	No	Partial	Yes	Yes	Yes
Neon and Floating Point Unit	Optional	Optional	Optional	Optional	Included
Floating Point Unit only	Optional	Optional	Optional	Optional	Included
Cryptography Unit	No	No	No	No	No
Physical Addressing (PA)	32-bit	40-bit	32-bit	40-bit	40-bit
Dual Core Lock-Step (DCLS)	No	No	No	No	No
L1 I-Cache / D-Cache	4k-64k	8k-64k	16k-64k	32kB/32kB	32k-64k/32k
L2 Cache	External L2C-310	Up to 1MB	External L2C-310	512kB-4MB	256kB-8MB
L3 Cache	NA	NA	NA	NA	NA
ECC / Parity		No	Yes	Yes	L2 only
LPAE	No	Yes	No	Yes	Yes
Bus Interfaces	AXI	ACE	AXI	ACE or CHI	ACE
ACP	Optional	No	Optional	Optional	Optional
Peripheral Port			No	No	Yes
Functional Safety Support
Security	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone
Interrupt Controller	Optional Integrated GIC v1 (MP only)	Optional Integrated GIC v2	Internal Integrated GIC v1 (MP only)	Optional Integrated GICv2	External GICv2
Generic Timer	No	Yes	Yes	Armv8-A	Armv8-A

Cortex-A comparison (Armv8-A)

Feature	Cortex-A32	Cortex-A34	Cortex-A35	Cortex-A53	Cortex-A55	Cortex-A57	Cortex-A65	Cortex-A65AE	Cortex-A72	Cortex-A73	Cortex-A75	Cortex-A76	Cortex-A76AE	Cortex-A77	Cortex-A78
Instruction set architecture and extensions	Armv8-A AArch32 only	Armv8-A AArch64 only	Armv8-A	Armv8-A	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only)	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A	Armv8-A	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline	In order	In order	In order	In order	In order	Out of order	Out of order	Out-of-order	Out of order	Out of order	Out-of-order	Out-of-order	Out-of-order	Out-of-order	Out-of-order
Superscalar				Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Neon and Floating Point Unit	Optional	Optional	Optional	Optional	Optional	Included	Included	Included	Included	Included	Included	Included	Included	Included	Included
Floating Point Unit only	N/A	N/A	N/A	N/A	Optional	Included	Included	Included	Included	Included	Included	Included	Included	Included	Included
Cryptography Unit	Optional	Optional	Optional	Optional	N/A	Optional	Optional	Optional	Optional	Optional	Optional	Optional	Optional	Optional	Optional
Physical Addressing (PA)	40-bit	40-bit	40-bit	40-bit	40-bit	40-bit	44-bit	44-bit	44-bit	40-bit	44-bit	40-bit	40-bit	40-bit	40-bit
Dual Core Lock-Step (DCLS)	No	No	No	No	No	No	No	Yes (in safety-mode)	No	No	No	No	Yes (in safety-mode)	No	No
L1 I-Cache / D-Cache	8k-64k	8k-64k	8k-64k	8k-64k	16kB-64kB	48kB/32kB	16KB to 64KB	16KB to 64KB	48KB/32kB-64kB	32k/32k-64k	64KB	64KB	64KB	64KB	64KB
L2 Cache	128KB-1MB	128KB-1MB	128KB-1MB	128KB-2MB	64kB-256kB	512kB-2MB	64KB to 256KB	64KB to 256KB	512kB-4MB	256k-8MB	256KB to 512KB	256KB to 512KB	256KB to 512KB	256KB to 512KB	256KB to 512KB
L3 Cache	NA	NA	NA	NA	Optional From 256kB to 4MB	NA	Optional 512KB to 4MB	Optional 512KB to 4MB	NA	NA	Optional 512KB to 4MB	Optional 512KB to 4MB	Optional 512KB to 4MB	Optional 512KB to 4MB	Optional 512KB to 4MB
ECC / Parity	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	L2 only	Yes	Yes	Yes	Yes	Yes
LPAE	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Bus Interfaces	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI
ACP	Optional	Optional	Optional	Optional	Optional	Yes	Optional	Optional	Optional	Yes	Optional	Optional	Optional	Optional	Optional
Peripheral Port					Optional		Optional	Optional			Optional	Optional	Optional	Optional	Optional
Functional Safety Support	Yes	Yes	Yes	Yes	Yes	Yes		Yes	Yes		Yes	Yes	Yes	Yes	ASIL D systematic
Security	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone
Interrupt Controller	External GICv3	External GICv3	External GICv3	External GICv3	External GICv4	External GICv3	External GICv4	External GICv4	External GICv3	External GICv3	External GICv4	External GICv4	External GICv4	External GICv4	External GICv4
Generic Timer	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A

Related IP

The Cortex-A15 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A15 processor is fully supported by Arm development tools. Related IP includes:

Graphic IP

Other IP

Tools

Mali-450 GPU

Mali Display Processors

Mali-V500 Video-Processor

CoreLink Cache Coherent Interconnect Family

Memory Controllers

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

Community Blogs

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5 years ago by Song Bin 宋斌

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5 years ago by wangyong

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Cortex-A15

The Cortex-A15 is a high-performance processor that implements the Armv7-A architecture.

Getting Started

Specifications

Looking for more information on Arm Cortex-A15?

Characteristics

Cortex-A15 Technical Reference Manual

Cortex-A Series Programmer's Guide for Armv7-A

Development Tools for Cortex-A

Cortex-A comparison table (Armv7-A)

Cortex-A comparison (Armv8-A)

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Related IP

Community Blogs

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