Cortex-A17

The Arm Cortex-A17 processor is the highest performance Armv7-A processor.

Information on Cortex-A17.

Getting Started

The Arm Cortex-A17 processor offers 60% more single thread performance over the Cortex-A9 in a power and area-efficient package, which makes it ideal for mid-range solutions. The processor includes the latest Armv7-A features such as virtualization support, Large Physical Addressing Extension (LPAE), Neon and 128-bit ACE interface.

Specifications

Architecture Armv7-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology. Compatible with CCI-400 for up to two clusters.
ISA Support
  
  • Arm and Thumb-2
  • TrustZone security technology
  • Neon Advanced SIMD
  • DSP & SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
  • Large Physical Address Extensions (LPAE)
  • Integer Divide
  • Fused MAC
  • Hypervisor debug instructions
Memory Management Unit (MMU)
 Armv7 Memory Management Unit
Debug & Trace
 CoreSight

Looking for more information on Arm Cortex-A17

Get in touch to speak with one of our technical experts.

Contact us

Characteristics

 The Cortex-A17 processor is optimized for maximum performance for mobile mid-range power budgets. With 60% more single thread performance over the Cortex-A9 processor, the Cortex-A17 processor is the fastest mid-range solution available.

Additionally, the Cortex-A17 processor offers 50% performance uplift over Cortex-A9 on Neon and FPU workloads, boosting performance of any code leveraging this capability such as audio and video codecs.

With expected frequencies beyond 2.5GHz in 28nm, the Cortex-A17 processor can be scaled in size to meet a range of different application demands. Topologies are expected to vary depending on the use case due to the malleability of the Cortex-A17 processor.

  • Manual containing technical information.

  • Cortex-A17 Technical Reference Manual

    The complete guide for system designers, integrators and programmers working on Cortex-A17 based System-on-Chips.

    Read here
  • A program that is running on a desktop.

  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.

  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB		 NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3		 External
GICv3		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv4		 External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A17 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Related IP

The Cortex-A17 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A17 processor is fully supported by Arm development tools. Related IP includes:

 

Graphic IP
 Other IP
 Tools

Mali-450 GPU

Mali Display Processors

Mali-V500 Video Processor

CoreLink Interconnect

Interrupt Controllers

CoreLink System Controllers

CoreLink DMC-500 and CoreLink DMC-520

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

 

Community Blogs

Blog post image
EW17 DEMO: How to build a robot

You may not be able to teach a robot how to love yet, but you can teach it how to play retro arcade games. It wasn’t so long ago that robots were the preserve of Sci-Fi films and now we are approaching an era where they can interact alongside h

2 years ago by Edd Duthie
Blog post image
应用笔记: big.LITTLE系统电源管理注意事项概述

在SoC设计中，电源管理比较重要，而且变得越来越复杂，比较容易出错。最近，我们写了一篇关于big.LITTLE系统电源管理注意要点的一篇应用笔记，希望对大家能有参考价值。 目的对big.LITTLE的电源管理需要注意事项进行概述，旨在帮助您在big.LITTLE的设计中避免一些潜在的问题。目标读者本文目标读者是, 基于ARM架构的SoC的设计者。本文默认您具有SoC设计的经验，并熟悉ARM的产品。范围本文适用范围包含以下处理器：.Cortex®-A7.Cortex®-A15.

3 years ago by Roy Hu
Blog post image
Application Note: High-level Considerations for Power Management of a…

Power management is important, and has become increasingly complex. Recently, we have created an application note. See details below. Hopefully, you will find it useful.PurposeProvides high-level considerations for power management of a big.LITTLE sy

3 years ago by Roy Hu
1
Blog post image
Chromebit棒状电脑，使用瑞芯微的RK3288-C芯片

今天看到合作伙伴瑞芯微 Rockchip 发表的博客，有关RK3288-C（Cortex-A17, Mali-T760)应用于最新的Chromebit。感觉今后可能是一个很好的卖点。大家对于随身携带笔记本电脑已经有些厌烦了，我个人就最不喜欢出门背着我的ThinkPad. 如果今后所有的电脑都能简化到一个U盘这么大就好了。外设的屏幕和键盘等输入设备都可以另接，或者使用卷曲键盘和类似于戒指或者手镯的新式鼠标，那么出行就能更方便。当然，可能今后手机也能完成目前笔记本电脑所做的大部分工作。便携式电脑和手

4 years ago by Song Bin 宋斌
Blog post image
Cortex-A17 powers new generation of Chrome OS devices

Last week, several of our partners unveiled new Chrome OS devices powered by Cortex-A17 based processor. These new products include two Chromebooks from Haier and HiSense at very competitive low price, a convertible laptop-tablet called the Chromeboo

4 years ago by Lionel Belnet
Blog post image
瑞芯微Google携手向全球发布新一代Chrome OS笔记本处理器产品

美国太平洋时间2015年3月31日10点15分，瑞芯微向全球发布新一代笔记本处理器RK3288-C,并联合Google同时发布了与华硕、海尔、海信合作的一系列内置瑞芯微芯片处理器的Chrome OS终端产品。至此，中国芯首次入主全球PC市场！  此次搭载瑞芯微RK3288-C笔记本处理器的六款Chrome OS新一代产品，除了常规笔记本形态外，还包括全球首款可360°翻转的笔记本和全球第一款“棒棒”形态的Chrome OS终端：五款新型Chromebo

4 years ago by wangyong

Community Forums

Not answered Hello! I´m new with stm mcu´s and I would like to know how to generate a 10ns pulse with stm32f407 discovery kit. Is it possible? 0 votes 13 views 0 replies Started 6 hours ago by Analog Answer this
Answered hardfault error
  • Cortex-M4
 0 votes 938 views 4 replies Latest 3 days ago by 42Bastian Schick Answer this
Suggested answer Can I run an A9 program under A53 without any modification 0 votes 1050 views 1 replies Latest 4 days ago by 42Bastian Schick Answer this
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) 0 votes 255 views 2 replies Latest 4 days ago by qinwenjian Answer this
Answered MPS2+ Expansion ports possible frequency and usage
  • ANSI
  • FPGA
  • iOS
  • Cortex-M
  • Cortex-M Prototyping System (V2M-MPS2)
 0 votes 3521 views 6 replies Latest 4 days ago by kfzhang Answer this
Not answered There was a problem compiling the content above design start eval. 1 votes 87 views 0 replies Started 5 days ago by qinwenjian Answer this
Not answered Hello! I´m new with stm mcu´s and I would like to know how to generate a 10ns pulse with stm32f407 discovery kit. Is it possible? Started 6 hours ago by Analog 0 replies 13 views
Answered hardfault error Latest 3 days ago by 42Bastian Schick 4 replies 938 views
Suggested answer Can I run an A9 program under A53 without any modification Latest 4 days ago by 42Bastian Schick 1 replies 1050 views
Suggested answer what can I get from cortex M0 design start pro?Whether I can get the RTL describle of Cortex M0(not obfuscated RTL) Latest 4 days ago by qinwenjian 2 replies 255 views
Answered MPS2+ Expansion ports possible frequency and usage Latest 4 days ago by kfzhang 6 replies 3521 views
Not answered There was a problem compiling the content above design start eval. Started 5 days ago by qinwenjian 0 replies 87 views