Cortex-A17

Specifications

Architecture	Armv7-A
Multicore	1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 ACE technology. Compatible with CCI-400 for up to two clusters.
ISA Support	Arm and Thumb-2 TrustZone security technology Neon Advanced SIMD DSP & SIMD extensions VFPv4 Floating point Hardware virtualization support Large Physical Address Extensions (LPAE) Integer Divide Fused MAC Hypervisor debug instructions
Memory Management Unit (MMU)	Armv7 Memory Management Unit
Debug & Trace	CoreSight

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Characteristics

The Cortex-A17 processor is optimized for maximum performance for mobile mid-range power budgets. With 60% more single thread performance over the Cortex-A9 processor, the Cortex-A17 processor is the fastest mid-range solution available.

Additionally, the Cortex-A17 processor offers 50% performance uplift over Cortex-A9 on Neon and FPU workloads, boosting performance of any code leveraging this capability such as audio and video codecs.

With expected frequencies beyond 2.5GHz in 28nm, the Cortex-A17 processor can be scaled in size to meet a range of different application demands. Topologies are expected to vary depending on the use case due to the malleability of the Cortex-A17 processor.

Cortex-A17 Technical Reference Manual

The complete guide for system designers, integrators and programmers working on Cortex-A17 based System-on-Chips.
Read here
Cortex-A Series Programmer's Guide for Armv7-A

Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

Get the guide
Development Tools for Cortex-A

Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

Learn more

Cortex-A comparison table (Armv7-A)

Feature	Cortex-A5	Cortex-A7	Cortex-A9	Cortex-A15	Cortex-A17
Instruction set architecture and extensions	Armv7-A	Armv7-A LPAE Virtualization	Armv7-A	Armv7-A LPAE Virtualization	Armv7-A LPAE Virtualization
Pipeline	In order	In order	Out of order	Out of order	Out of order
Superscalar	No	Partial	Yes	Yes	Yes
Neon and Floating Point Unit	Optional	Optional	Optional	Optional	Included
Floating Point Unit only	Optional	Optional	Optional	Optional	Included
Cryptography Unit	No	No	No	No	No
Physical Addressing (PA)	32-bit	40-bit	32-bit	40-bit	40-bit
Dual Core Lock-Step (DCLS)	No	No	No	No	No
L1 I-Cache / D-Cache	4k-64k	8k-64k	16k-64k	32kB/32kB	32k-64k/32k
L2 Cache	External L2C-310	Up to 1MB	External L2C-310	512kB-4MB	256kB-8MB
L3 Cache	NA	NA	NA	NA	NA
ECC / Parity		No	Yes	Yes	L2 only
LPAE	No	Yes	No	Yes	Yes
Bus Interfaces	AXI	ACE	AXI	ACE or CHI	ACE
ACP	Optional	No	Optional	Optional	Optional
Peripheral Port			No	No	Yes
Functional Safety Support
Security	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone
Interrupt Controller	Optional Integrated GIC v1 (MP only)	Optional Integrated GIC v2	Internal Integrated GIC v1 (MP only)	Optional Integrated GICv2	External GICv2
Generic Timer	No	Yes	Yes	Armv8-A	Armv8-A

Cortex-A comparison (Armv8-A)

Feature	Cortex-A32	Cortex-A34	Cortex-A35	Cortex-A53	Cortex-A55	Cortex-A57	Cortex-A65	Cortex-A65AE	Cortex-A72	Cortex-A73	Cortex-A75	Cortex-A76	Cortex-A76AE	Cortex-A77	Cortex-A78
Instruction set architecture and extensions	Armv8-A AArch32 only	Armv8-A AArch64 only	Armv8-A	Armv8-A	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only)	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A	Armv8-A	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product	Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline	In order	In order	In order	In order	In order	Out of order	Out of order	Out-of-order	Out of order	Out of order	Out-of-order	Out-of-order	Out-of-order	Out-of-order	Out-of-order
Superscalar				Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Neon and Floating Point Unit	Optional	Optional	Optional	Optional	Optional	Included	Included	Included	Included	Included	Included	Included	Included	Included	Included
Floating Point Unit only	N/A	N/A	N/A	N/A	Optional	Included	Included	Included	Included	Included	Included	Included	Included	Included	Included
Cryptography Unit	Optional	Optional	Optional	Optional	N/A	Optional	Optional	Optional	Optional	Optional	Optional	Optional	Optional	Optional	Optional
Physical Addressing (PA)	40-bit	40-bit	40-bit	40-bit	40-bit	40-bit	44-bit	44-bit	44-bit	40-bit	44-bit	40-bit	40-bit	40-bit	40-bit
Dual Core Lock-Step (DCLS)	No	No	No	No	No	No	No	Yes (in safety-mode)	No	No	No	No	Yes (in safety-mode)	No	No
L1 I-Cache / D-Cache	8k-64k	8k-64k	8k-64k	8k-64k	16kB-64kB	48kB/32kB	16KB to 64KB	16KB to 64KB	48KB/32kB-64kB	32k/32k-64k	64KB	64KB	64KB	64KB	64KB
L2 Cache	128KB-1MB	128KB-1MB	128KB-1MB	128KB-2MB	64kB-256kB	512kB-2MB	64KB to 256KB	64KB to 256KB	512kB-4MB	256k-8MB	256KB to 512KB	256KB to 512KB	256KB to 512KB	256KB to 512KB	256KB to 512KB
L3 Cache	NA	NA	NA	NA	Optional From 256kB to 4MB	NA	Optional 512KB to 4MB	Optional 512KB to 4MB	NA	NA	Optional 512KB to 4MB	Optional 512KB to 4MB	Optional 512KB to 4MB	Optional 512KB to 4MB	Optional 512KB to 4MB
ECC / Parity	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	L2 only	Yes	Yes	Yes	Yes	Yes
LPAE	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Bus Interfaces	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI	ACE or CHI
ACP	Optional	Optional	Optional	Optional	Optional	Yes	Optional	Optional	Optional	Yes	Optional	Optional	Optional	Optional	Optional
Peripheral Port					Optional		Optional	Optional			Optional	Optional	Optional	Optional	Optional
Functional Safety Support	Yes	Yes	Yes	Yes	Yes	Yes		Yes	Yes		Yes	Yes	Yes	Yes	ASIL D systematic
Security	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone	TrustZone
Interrupt Controller	External GICv3	External GICv3	External GICv3	External GICv3	External GICv4	External GICv3	External GICv4	External GICv4	External GICv3	External GICv3	External GICv4	External GICv4	External GICv4	External GICv4	External GICv4
Generic Timer	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A	Armv8-A

Related IP

The Cortex-A17 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A17 processor is fully supported by Arm development tools. Related IP includes:

Graphic IP

Other IP

Tools

Mali-450 GPU

Mali Display Processors

Mali-V500 Video Processor

CoreLink Interconnect

Interrupt Controllers

CoreLink System Controllers

CoreLink DMC-500 and CoreLink DMC-520

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

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Community Forums

Not answered	System wide cache flush Cortex-A35 Cache coherency Armv8-A Cache Management	21 views	0 replies	Started 7 hours ago by M. Elsayed Badawy	Answer this
Answered	ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell	1432 views	3 replies	Latest 12 hours ago by jpthibault	Answer this
Not answered	Trouble configuring MMU for 2MB block mapping Memory Management Unit (MMU)	422 views	0 replies	Started yesterday by jcal93	Answer this
Suggested answer	Exec latency for ASIMD instructions taking the V pipelines	541 views	2 replies	Latest yesterday by sjub	Answer this
Suggested answer	floating point performance benchmark	1124 views	1 replies	Latest yesterday by sjub	Answer this
Answered	Cortex A53 Bare metal booting have FIQ exception. How to debug? Cortex-A53 CoreSight Architecture Baremetal	511 views	1 replies	Latest yesterday by Ben Chen	Answer this

Not answered	System wide cache flush Started 7 hours ago by M. Elsayed Badawy	0 replies 21 views
Answered	ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell Latest 12 hours ago by jpthibault	3 replies 1432 views
Not answered	Trouble configuring MMU for 2MB block mapping Started yesterday by jcal93	0 replies 422 views
Suggested answer	Exec latency for ASIMD instructions taking the V pipelines Latest yesterday by sjub	2 replies 541 views
Suggested answer	floating point performance benchmark Latest yesterday by sjub	1 replies 1124 views
Answered	Cortex A53 Bare metal booting have FIQ exception. How to debug? Latest yesterday by Ben Chen	1 replies 511 views

Cortex-A17

The Arm Cortex-A17 processor is the highest performance Armv7-A processor.

Getting Started

Specifications

Looking for more information on Arm Cortex-A17

Characteristics

Cortex-A17 Technical Reference Manual

Cortex-A Series Programmer's Guide for Armv7-A

Development Tools for Cortex-A

Cortex-A comparison table (Armv7-A)

Cortex-A comparison (Armv8-A)

Get Support

Related IP

Community Blogs

Community Forums