The Cortex-A32 processor uses an efficient, 8-stage, in-order pipeline that has been extensively optimized to provide the 32-bit Armv8-A features in the smallest footprint and power.
|Extensions||Armv8-A Cryptographic Extension|
|Multicore||1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology
|Debug and Trace
|Reference package or system example
Compare the specifications of Cortex-A Armv7-A and Armv8-A processors:
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Armv8-A Cryptographic Extension
The Armv8 Cryptographic Extension provides instructions for the acceleration of encryption and decryption, and includes:
- Armv8.0-AES, which includes AESD and AESE instructions.
- Armv8.0-SHA, which includes the SHA1* and SHA256* instructions.
The presence of the Cryptographic Extension in an implementation is subject to export license controls. The Cryptographic Extension is an extension of the SIMD support and operates on the vector register file
The Cryptographic Extension also provides multiply instructions that operate on long polynomials. The Cryptographic Extension provides this functionality in AArch64 state and AArch32 state, and an implementation that supports both AArch64 state and AArch32 state provides the same Cryptographic Extension functionality in both states.
The Cortex-A32 processor delivers higher efficiency (performance per mW) and higher performance than the Cortex-A7 and Cortex-A5 processors.
The graph depicts relative performance improvements delivered by the Cortex-A32 processor compared to the Cortex-A5 and Cortex-A7 processors across some of the popular benchmarks. The performance comparisons are for the same clock frequency and same processor configurations.