The Cortex-A34 processor is the smallest and most power-efficient 64-bit Armv8-A application processor.

About the Cortex-A34

The Cortex-A34 processor uses an efficient, 8-stage, in-order pipeline that has been extensively optimized to provide the 64-bit Armv8-A features in the smallest footprint and power.


Specifications

Architecture 64-Bit Armv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology
ISA Support
 
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • Neon Advanced SIMD
  • DSP and SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
Debug & Trace
CoreSight SoC-400

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Armv8-A Cryptographic Extension

The Armv8 Cryptographic Extension provides instructions for the acceleration of encryption and decryption, and includes:

  • Armv8.0-AES, which includes AESD and AESE instructions.
  • Armv8.0-SHA, which includes the SHA1* and SHA256* instructions.

The presence of the Cryptographic Extension in an implementation is subject to export license controls. The Cryptographic Extension is an extension of the SIMD support and operates on the vector register file

The Cryptographic Extension also provides multiply instructions that operate on long polynomials. The Cryptographic Extension provides this functionality in AArch64 state and AArch32 state, and an implementation that supports both AArch64 state and AArch32 state provides the same Cryptographic Extension functionality in both states.


  • A program that is running on a desktop.
  • Learn the Armv8-A architecture

    Common to all Cortex-A series processors, these guides are useful for anyone developing assembly and C language applications for Armv8-A.

    Read the guides
  • Architecture A 62 guide
  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

Cortex-A comparison table (Armv7-A)
Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A
Cortex-A comparison table (Armv8-A)
Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 44-bit 40-bit 44-bit 40-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB

L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB

L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB

ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes

LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI

ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional

Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional

Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes

Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone

Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
External
GICv4

Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

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Community Forums

Suggested answer compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application)
  • Cortex-A53
  • AArch64
  • Optimization Solution
  • Armv8-A
  • GCC
  • NEON
0 votes 156 views 2 replies Latest 12 hours ago by khan777 Answer this
Not answered Optimization of Neon Intrinsics on ARM cortexa53
  • Cortex-A53
  • AArch64
  • Optimization Solution
  • GCC
  • NEON
  • Arm Assembly Language (ASM)
0 votes 65 views 0 replies Started 14 hours ago by khan777 Answer this
Suggested answer Problem in understanding behaviour of GCC compiler (aarch64-none-elf-gcc) on Neon intrinsics for ARM cortex a53
  • Cortex-A53
  • Optimization Solution
  • GNU Assembler
  • GCC
  • NEON
  • Compilers
1 votes 3194 views 10 replies Latest 15 hours ago by khan777 Answer this
Not answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR)
  • CoreSight Architecture
  • Cortex-M
  • Debugging
  • CoreSight
  • Cortex-M4
0 votes 197 views 0 replies Started 21 hours ago by schroedingers_katze Answer this
Answered Cortex M0 - Returning from Interrupt
  • Cortex-M0
  • Arm Education Media
0 votes 1491 views 13 replies Latest yesterday by Mezan1 Answer this
Not answered How Can I jump from EL1 to EL0 in bare metal environment
  • EL1
  • ARMv8 Exception Model
  • EL0
  • Armv8-A
  • Arm64
0 votes 277 views 0 replies Started 2 days ago by Awax Answer this
Suggested answer compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application) Latest 12 hours ago by khan777 2 replies 156 views
Not answered Optimization of Neon Intrinsics on ARM cortexa53 Started 14 hours ago by khan777 0 replies 65 views
Suggested answer Problem in understanding behaviour of GCC compiler (aarch64-none-elf-gcc) on Neon intrinsics for ARM cortex a53 Latest 15 hours ago by khan777 10 replies 3194 views
Not answered timestamp generator register location on Cortex-M4 (PSELCTRL CNTCR) Started 21 hours ago by schroedingers_katze 0 replies 197 views
Answered Cortex M0 - Returning from Interrupt Latest yesterday by Mezan1 13 replies 1491 views
Not answered How Can I jump from EL1 to EL0 in bare metal environment Started 2 days ago by Awax 0 replies 277 views