Cortex-A35

The Cortex-A35 processor is Arm’s most power-efficient application processor capable of seamlessly supporting 32-bit and 64-bit code.

Information on Cortex-A35.

Getting Started

The Cortex-A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.

Specifications

Architecture 64-Bit Armv8-A
Multicore 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology
ISA Support
  
  • AArch32 for full backward compatibility with Armv7
  • AArch64 for 64-bit support and new architectural features
  • TrustZone security technology
  • Neon Advanced SIMD
  • DSP and SIMD extensions
  • VFPv4 Floating point
  • Hardware virtualization support
Debug & Trace
 CoreSight SoC-400

Start designing now

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Learn more

  • Manual containing technical information.

  • Cortex-A35 Technical Reference Manual

    For system designers and software engineers, the Cortex-A35 manual provides information on implementing and programming Cortex-A35 based devices.

    Read here
  • A program that is running on a desktop.

  • Learn the Armv8-A architecture

    Common to all Cortex-A series processors, these guides are useful for anyone developing assembly and C language applications for Armv8-A.

    Read the guides
  • Architecture A 62 guide

  • Porting to Arm 64-bit

    If you are migrating from an Armv7 architecture based design to the Armv8 64-bit A64 instruction set, we provide a porting guide to help you.

    Get the guide
  • a ulink, a board, a desktop.

  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more
  • A manual that contains information on safety.

  • Cortex-A Safety Documents Package

    For customers who needs to safety certify their end products, Arm provides a Safety Documentation Package for silicon developers and safety certified toolchain to accelerate the time to market.

    Read here
Cortex-A comparison table (Armv7-A)
Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A Armv7-A
LPAE Virtualization		 Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A comparison (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE Cortex-A77 Cortex-A78
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
 Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order Out-of-order
 Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
 Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included Included
 Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included
 Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional Optional
 Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 44-bit 40-bit 44-bit 40-bit 40-bit 40-bit
 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode) No
 No
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB 64KB
 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB 256KB to 512KB
 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB		 NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
 Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes Yes
 Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
 Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI
 ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional
 Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional Optional
 Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes Yes
 ASIL D systematic
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
 TrustZone
Interrupt Controller External
GICv3		 External
GICv3		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv3		 External
GICv3		 External
GICv4		 External
GICv4		 External
GICv4		 External
GICv4
 External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A
 Armv8-A

 

Related IP

The Cortex-A35 can be incorporated into a SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A35 processor is fully supported by Arm development tools. Related IP includes:

Graphic IP
 Other IP
 Tools

Mali-T820 and Mali-T830 GPUs

Mali-DP550 display processor

Mali-V550 video processor

CoreLink Interconnect

Interrupt Controllers

CoreLink Cache Coherent Interconnect Family

TrustZone CryptoCell

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fast Models

Development Boards

ARM Compiler

Fixed Virtual Platforms

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Suggested answer translation table APTable permission problem
  • Cortex-A57
  • Armv8-A
  • Linux
 0 votes 264 views 2 replies Latest 18 hours ago by raks8877 Answer this
Not answered Regarding Visibility of Multi Master ACE-Lite System 0 votes 231 views 0 replies Started yesterday by RajaAC Answer this
Not answered Cortex-M3 softcore minimal SoC
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 0 votes 41 views 0 replies Started yesterday by TinyLabs Answer this
Not answered Bus Fault when configuring cross trigger matrix / CTICONTROL 0 votes 93 views 0 replies Started yesterday by Jacek Wywrót Answer this
Answered which is better for performance fetching instructions from flash or SRAM? 0 votes 301 views 4 replies Latest 2 days ago by Andy Neil Answer this
Suggested answer the linux kernel will be hung here as long as there are more than one core inside one cluster 0 votes 4962 views 1 replies Latest 3 days ago by Zhifei Yang Answer this
Suggested answer translation table APTable permission problem Latest 18 hours ago by raks8877 2 replies 264 views
Not answered Regarding Visibility of Multi Master ACE-Lite System Started yesterday by RajaAC 0 replies 231 views
Not answered Cortex-M3 softcore minimal SoC Started yesterday by TinyLabs 0 replies 41 views
Not answered Bus Fault when configuring cross trigger matrix / CTICONTROL Started yesterday by Jacek Wywrót 0 replies 93 views
Answered which is better for performance fetching instructions from flash or SRAM? Latest 2 days ago by Andy Neil 4 replies 301 views
Suggested answer the linux kernel will be hung here as long as there are more than one core inside one cluster Latest 3 days ago by Zhifei Yang 1 replies 4962 views