Cortex-A5

The Cortex-A5 processor is the smallest, lowest power Armv7 application processor.

Information on Cortex-A5.

Getting Started

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.

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Fast, low-cost access to Cortex-A5 through Arm DesignStart.

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Specifications

Architecture Armv7-A
Multicore 1-4 cores
ISA Support
Memory Management Unit (MMU) Armv7 Memory Management Unit
Debug & Trace CoreSight

Characteristics

The Cortex-A5 is the smallest and lowest power applications processor, delivering rich functionality to high-performance, power-sensitive devices.

The processor’s small physical size also means reduced manufacturing costs, reduced system leakage and increased low-cost integration. Compared to the Cortex-A9 processor, the Cortex-A5 achieves more than 50% power efficiency while maintaining around 70-75% of the same performance level, making it ideal for wearable technology.

The Cortex-A5 processor is designed to be a highly configurable processor. The instruction and data cache sizes, for example, can be configured from a 64KB maximum size to as small as 4KB for cost-sensitive applications requiring a small application processor with a Memory Management Unit (MMU).

Performance comparison graph on Cortex-A5 and Cortex-A9.


  • Manual containing technical information.
  • Cortex-A5 Technical Reference Manual

    The main resource for hardware and software engineers implementing the Cortex-A5 processor in system designs.

    Read here
  • A program that is running on a desktop.
  • Cortex-A Series Programmer's Guide for Armv7-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv7-A.

    Get the guide
  • a ulink, a board, a desktop.
  • Development Tools for Cortex-A

    Arm and our partners provide specialist code generation, debug and analysis tools for software development on Cortex-A series processors, such as DS-5 Development Studio.

    Learn more

Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode)
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

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Related IP

The Cortex-A5 processor can be incorporated into an SoC using a broad range of Arm technology including Graphics IP, System IP, and Physical IP. The Cortex-A5 processor is fully supported by Arm development tools. Related IP includes:

Graphic IP
Other IP
Tools

Mali-400 GPU

CoreLink Network Interconnect Family

CoreLink System Controllers

Interrupt Controllers

CoreSight SoC-400

POP IP

DS-5 Development Studio

Fixed Virtual Platforms

Development Boards

Arm Compiler

Fast Models

The Cortex-A5 also offers other configurability options such as optional Floating-Point Unit (FPU) and Neon which enable designers to make trade-offs for performance and cost in their targeted application. In its smallest possible configuration with 4KB caches, the Cortex-A5 can be just 0.2mm2 in size at 28nm process technology.

Community Blogs

Community Forums

Not answered Trigger a Software Interrupt 0 votes 13 views 0 replies Started 8 hours ago by Aquox Answer this
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil
  • R15 (PC Program Counter)
  • Cortex-M1
  • R13 (SP Stack Pointer)
  • Keil
0 votes 108 views 3 replies Latest 12 hours ago by 42Bastian Schick Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 45 views 0 replies Started 2 days ago by jing Answer this
Answered Binary Semaphore upset by FIQ
  • Cortex-A
0 votes 873 views 20 replies Latest 4 days ago by 42Bastian Schick Answer this
Not answered Identifying Generic IP Components on an Access Port 0 votes 65 views 0 replies Started 5 days ago by Torsten Robitzki Answer this
Not answered Issue with WatchDog reset De-asserting 0 votes 69 views 0 replies Started 5 days ago by BAB Answer this
Not answered Trigger a Software Interrupt Started 8 hours ago by Aquox 0 replies 13 views
Suggested answer Modify SP register and PC register in Cortex-M1 using Keil Latest 12 hours ago by 42Bastian Schick 3 replies 108 views
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started 2 days ago by jing 0 replies 45 views
Answered Binary Semaphore upset by FIQ Latest 4 days ago by 42Bastian Schick 20 replies 873 views
Not answered Identifying Generic IP Components on an Access Port Started 5 days ago by Torsten Robitzki 0 replies 65 views
Not answered Issue with WatchDog reset De-asserting Started 5 days ago by BAB 0 replies 69 views