The Arm Cortex-A5 processor is the smallest application processor in the Cortex-A family of processors

The Cortex-A5 processor offers high performance with a low-power consumption, addressing a variety of feature-rich and Linux-capable embedded and IoT applications.

Information on Cortex-A5.
Architecture Armv7-A
Multicore 1-4 cores
Instruction Cache 4K-64K
Data Cache 4K-64K
Floating point unit Optional (VFPv4)
Neon, SIMD architecture instruction Optional
DSP extensions Optional
ETM Optional
ACP port Optional (only multi-processor)
Memory Management Unit (MMU) Armv7 Memory Management Unit
Debug and Trace CoreSight
Reference package or system example

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Performance comparison graph on Cortex-A5 and Cortex-A9.


The processor’s small physical size means reduced manufacturing costs, reduced system leakage and increased low-cost integration. Compared to the Cortex-A9 processor, the Cortex-A5 achieves more than 50% power efficiency while maintaining around 70-75% of the same performance level, making it ideal for wearable technology.

The Cortex-A5 processor is designed to be a highly configurable processor. The instruction and data cache sizes, for example, can be configured from a 64KB maximum size to as small as 4KB for cost-sensitive applications requiring a small application processor with a Memory Management Unit (MMU).


Advanced CPU

  • Up to 4x CPU cores for maximum performance and load sharing
  • Hardware coherency for easy data sharing
  • Advanced data processing with SIMD engine

High efficiency
Small footprint for minimal power consumption

AMBA standards

  • AXI3 bus interfaces
  • Coresight debug and trace

Easy integration of accelerators
High performance Advanced Accelerator Port (ACP) for fast connection to machine learning and custom accelerators

Hardware security with Arm TrustZone technology
Industry proven security built into the CPU

Memory Management Unit (MMU)
Supports rich operating systems including Linux, with an Armv7 MMU

Highly configurable to address diverse requirements
For example, the following diagrams show possible configurations:

Area and power-optimized configuration

Performance-optimized, multi-core configuration