The Cortex-A510 CPU is the first generation Armv9 high-efficiency "LITTLE" CPU based on Arm DynamIQ Technology.
Cortex-A510 is an Armv9 CPU designed for efficient performance and provides scalable features to target a broad range of devices from smart watches to mobile. Cortex-A510 provides up to 35% performance uplift over its predecessor Cortex-A55, along with up to 3x machine learning uplift. Introducing a grounds-up design with merged-core microarchitecture, which allows two Cortex-A510 cores to be grouped into a complex. Multiple Cortex-A510 complexes can be paired with Cortex-X2 and Cortex-A710 in a DynamIQ big.LITTLE configuration for scalability across multiple target markets.
Arm is focused on delivering a Total Compute solution for the ecosystem, including enhanced Cortex-X and Cortex-A CPUs, Mali GPUs, Ethos NPUs, CoreLink and CoreSight System IP.
Arm Cortex-A510 CPU
Up to Armv8.5 extensions
|Neon / Floating Point Unit / SVE2||Included|
|Max number of CPUs in cluster
|Physical Addressing (PA)
|Core architecture||Merged-core, up to 2 cores per complex
|Memory system and external interfaces
||L1 I-Cache / D-Cache||32KB or 64KB|
|L2 Cache||Optional, 128KB, 192KB, 256KB, 384KB, 512KB|
|L3 Cache||Optional, 256KB to 16MB|
|Bus interfaces||AMBA AXI5 or CHI.E|
|Interrupts||GIC interface, GICv4.1|
|Embedded Trace Extension||ETEv1.0|
|Trace Buffer Extension||Yes|
Compare the specifications of Cortex-A Armv7-A and Armv8-A processors:
Key benefits of Cortex-A510
- Supports Armv9 features across performance, security and machine learning. Key features are SVE2, MTE, PAC, BTI, Secure EL2, support for BFloat16 format and Matrix Multiply instructions for the Int8 and BFloat16
- CPU integer performance uplift of up to 35%
- Improvement of up to 20% in CPU energy efficiency at the peak performance of Cortex-A55
- Up to 300% improvement in machine learning workload performance over Cortex-A55