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We are making some changes to the way you raise support cases
The Cortex-A53 processor is a high efficiency processor that implements the Armv8-A architecture.
The Cortex-A53 processor has one to four cores, each with an L1 memory system and a single shared L2 cache. It can be combined with other Cortex-A CPUs in a big.LITTLE configuration.

Arm Cortex-A53 CPU
| Architecture | Armv8-A |
| Multicore | 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology |
| ISA Support |
|
| Debug & Trace |
|
The Armv8 Cryptographic Extension provides instructions for the acceleration of encryption and decryption, and includes:
The presence of the Cryptographic Extension in an implementation is subject to export license controls. The Cryptographic Extension is an extension of the SIMD support and operates on the vector register file
The Cryptographic Extension also provides multiply instructions that operate on long polynomials. The Cryptographic Extension provides this functionality in AArch64 state and AArch32 state, and an implementation that supports both AArch64 state and AArch32 state provides the same Cryptographic Extension functionality in both states.
The Cortex-A53 processor delivers significantly more performance than its predecessors at a higher level of power efficiency. This takes the performance of the core above that of the Cortex-A7 processor, which defines many popular mainstream and entry-level mobile platforms. The performance graph to the right shows the performance improvements of the Cortex-A53 processor against the Cortex-A7 processor.
The Armv8-A architecture brings a number of new features. These include 64-bit data processing, extended virtual addressing and a 64-bit general purpose registers. The Cortex-A53 processor is Arm’s first Armv8-A processor aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dual-issue pipeline, and improved integer, Neon, Floating-Point Unit (FPU) and memory performance.
The Cortex-A53 can be implemented in two execution states: AArch32 and AArch64. The AArch64 state gives the Cortex-A53 its ability to execute 64-bit applications, while the AArch32 state allows the processor to execute existing Armv7-A applications.

Arm Flexible Access gives you quick and easy access to this IP, relevant tools and models, and valuable support. You can evaluate and design solutions before committing to production, and only pay when you are ready to manufacture.
| Feature | Cortex-A5 | Cortex-A7 | Cortex-A9 | Cortex-A15 | Cortex-A17 |
|---|---|---|---|---|---|
| Instruction set architecture and extensions | Armv7-A | Armv7-A LPAE Virtualization |
Armv7-A | Armv7-A LPAE Virtualization |
Armv7-A LPAE Virtualization |
| Pipeline | In order | In order | Out of order | Out of order | Out of order |
| Superscalar | No | Partial | Yes | Yes | Yes |
| Neon and Floating Point Unit | Optional | Optional | Optional | Optional | Included |
| Floating Point Unit only | Optional | Optional | Optional | Optional | Included |
| Cryptography Unit | No | No | No | No | No |
| Physical Addressing (PA) | 32-bit | 40-bit | 32-bit | 40-bit | 40-bit |
| Dual Core Lock-Step (DCLS) | No | No | No | No | No |
| L1 I-Cache / D-Cache | 4k-64k | 8k-64k | 16k-64k | 32kB/32kB | 32k-64k/32k |
| L2 Cache | External L2C-310 | Up to 1MB | External L2C-310 | 512kB-4MB | 256kB-8MB |
| L3 Cache | NA | NA | NA | NA | NA |
| ECC / Parity | No | Yes | Yes | L2 only | |
| LPAE | No | Yes | No | Yes | Yes |
| Bus Interfaces | AXI | ACE | AXI | ACE or CHI | ACE |
| ACP | Optional | No | Optional | Optional | Optional |
| Peripheral Port | No | No | Yes | ||
| Functional Safety Support | |||||
| Security | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone |
| Interrupt Controller | Optional Integrated GIC v1 (MP only) | Optional Integrated GIC v2 | Internal Integrated GIC v1 (MP only) | Optional Integrated GICv2 | External GICv2 |
| Generic Timer | No | Yes | Yes | Armv8-A | Armv8-A |
| Feature | Cortex-A32 | Cortex-A34 | Cortex-A35 | Cortex-A53 | Cortex-A55 | Cortex-A57 | Cortex-A65 | Cortex-A65AE | Cortex-A72 | Cortex-A73 | Cortex-A75 | Cortex-A76 | Cortex-A76AE | Cortex-A77 | Cortex-A78 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Instruction set architecture and extensions | Armv8-A AArch32 only | Armv8-A AArch64 only | Armv8-A | Armv8-A | Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product | Armv8-A | Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) | Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product | Armv8-A | Armv8-A | Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product | Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product | Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product | Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product |
Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product |
| Pipeline | In order | In order | In order | In order | In order | Out of order | Out of order | Out-of-order | Out of order | Out of order | Out-of-order | Out-of-order | Out-of-order | Out-of-order |
Out-of-order |
| Superscalar | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Yes | |||
| Neon and Floating Point Unit | Optional | Optional | Optional | Optional | Optional | Included | Included | Included | Included | Included | Included | Included | Included | Included |
Included |
| Floating Point Unit only | N/A | N/A | N/A | N/A | Optional | Included | Included | Included | Included | Included | Included | Included | Included | Included |
Included |
| Cryptography Unit | Optional | Optional | Optional | Optional | N/A | Optional | Optional | Optional | Optional | Optional | Optional | Optional | Optional | Optional |
Optional |
| Physical Addressing (PA) | 40-bit | 40-bit | 40-bit | 40-bit | 40-bit | 40-bit | 44-bit | 44-bit | 44-bit | 40-bit | 44-bit | 40-bit | 40-bit | 40-bit |
40-bit |
| Dual Core Lock-Step (DCLS) | No | No | No | No | No | No | No | Yes (in safety-mode) | No | No | No | No | Yes (in safety-mode) | No |
No |
| L1 I-Cache / D-Cache | 8k-64k | 8k-64k | 8k-64k | 8k-64k | 16kB-64kB | 48kB/32kB | 16KB to 64KB | 16KB to 64KB | 48KB/32kB-64kB | 32k/32k-64k | 64KB | 64KB | 64KB | 64KB |
64KB |
| L2 Cache | 128KB-1MB | 128KB-1MB | 128KB-1MB | 128KB-2MB | 64kB-256kB | 512kB-2MB | 64KB to 256KB | 64KB to 256KB | 512kB-4MB | 256k-8MB | 256KB to 512KB | 256KB to 512KB | 256KB to 512KB | 256KB to 512KB |
256KB to 512KB |
| L3 Cache | NA | NA | NA | NA | Optional From 256kB to 4MB |
NA | Optional 512KB to 4MB | Optional 512KB to 4MB | NA | NA | Optional 512KB to 4MB | Optional 512KB to 4MB | Optional 512KB to 4MB | Optional 512KB to 4MB |
Optional 512KB to 4MB |
| ECC / Parity | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | L2 only | Yes | Yes | Yes | Yes |
Yes |
| LPAE | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
Yes |
| Bus Interfaces | ACE or CHI | ACE or CHI | ACE or CHI | ACE or CHI | ACE or CHI | ACE or CHI | ACE or CHI | ACE or CHI | ACE or CHI | ACE | ACE or CHI | ACE or CHI | ACE or CHI | ACE or CHI |
ACE or CHI |
| ACP | Optional | Optional | Optional | Optional | Optional | Yes | Optional | Optional | Optional | Yes | Optional | Optional | Optional | Optional |
Optional |
| Peripheral Port | Optional | Optional | Optional | Optional | Optional | Optional | Optional |
Optional | |||||||
| Functional Safety Support | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
ASIL D systematic | ||
| Security | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone | TrustZone |
TrustZone |
| Interrupt Controller | External GICv3 |
External GICv3 |
External GICv3 |
External GICv3 |
External GICv4 |
External GICv3 |
External GICv4 |
External GICv4 |
External GICv3 |
External GICv3 |
External GICv4 |
External GICv4 |
External GICv4 |
External GICv4 |
External GICv4 |
| Generic Timer | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A | Armv8-A |
Armv8-A |
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