Cortex-A55

Arm’s most power efficient mid-range application CPU built on Arm DynamIQ technology. 

Information on Cortex-A55.

Getting Started

The Arm Cortex-A55 processor is a market-leading CPU that delivers the best combination of power efficiency and performance in its class. It is part of the first generation of application CPUs based on DynamIQ technology and features the latest Armv8-A architecture extensions, with dedicated machine learning instructions. 

The Cortex-A55 incorporates an extensively redesigned microarchitecture system that improves performance across the board while being very competitive in area and power efficiency. It delivers up to 18% more performance at 15% better power efficiency when compared to its predecessor, the Cortex-A53. 

Designed to be an extremely scalable CPU, the versatile Cortex-A55 can be used to address a wide range of applications with diverging cost, from the edge to the cloud. The Cortex-A55 can be implemented in both stand-alone applications or as a ‘LITTLE’ CPU to the Cortex-A7x series with DynamIQ big.LITTLE.

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Specifications

General Architecture Armv8-A (Harvard)
  Extensions Armv8.1 extensions,
Armv8.2 extensions,
Cryptography extensions,
RAS extensions,
Armv8.3 (LDAPR instructions only)
  ISA Support A64, A32, and T32 instruction sets 
Microarchitecture Pipeline In-order
  Superscalar Yes
  Neon / Floating Point Unit  Optional
  Cryptography Unit
Optional
  Max Number of CPUs in Cluster Eight (8)
  Physical Addressing (PA) 40-bit
Memory System and External Interfaces L1 I-Cache / D-Cache 16KB to 64KB
  L2 Cache Optional, 64KB to 256KB
  L3 Cache Optional, 512KB to 4MB
  ECC Support Yes 
  LPAE Yes 
  Bus Interfaces ACE or CHI 
  ACP Optional 
  Peripheral Port Optional 
Other Functional Safety Support ASIL D systematic
  Security TrustZone 
  Interrupts GIC Interface, GICv4 
  Generic Timer  Armv8-A
  PMU PMUv3 
  Debug Armv8-A (plus Armv8.2-A extensions) 
  CoreSight CoreSightv3 
  Embedded Trace Macrocell ETMv4.2 (instruction trace)
  • Manual containing technical information.
  • The Cortex-A55 Technical Reference Manual

    For system designers, system integrators, and programmers who are designing a SoC, the Technical Reference Manual is the go-to resource.

    Read here
  • A guide on software optimization.
  • Cortex-A55 Software Optimization Guide

    For software engineers and programmers, the software optimization guide examines the performance characteristics of instructions in detail.

    Read here
  • A guide on software optimization.
  • Cortex-A Series Programmer's Guide for Armv8-A

    Common to all Cortex-A series processors, this programmer's guide is useful for assembly and C language application development for Armv8-A.

    Get the Guide
  • A manual that contains information on safety.
  • Cortex-A55 Safety Documents Package

    For customers who needs to safety certification for their end products, Arm provides a Safety Documentation Package for silicon developers and safety-certified toolchain to accelerate the time to market.

    Coming Soon


Cortex-A Comparison Table (Armv7-A)

Feature Cortex-A5 Cortex-A7 Cortex-A9 Cortex-A15 Cortex-A17
Instruction set architecture and extensions Armv7-A Armv7-A
LPAE Virtualization
Armv7-A Armv7-A
LPAE Virtualization
Armv7-A
LPAE Virtualization
Pipeline In order In order Out of order Out of order Out of order
Superscalar No Partial Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Included
Floating Point Unit only Optional Optional Optional Optional Included
Cryptography Unit No No No No No
Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No
L1 I-Cache / D-Cache 4k-64k 8k-64k 16k-64k 32kB/32kB 32k-64k/32k
L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB
L3 Cache NA NA NA NA NA
ECC / Parity   No Yes Yes L2 only
LPAE No Yes No Yes Yes
Bus Interfaces AXI ACE AXI ACE or CHI ACE
ACP Optional No Optional Optional Optional
Peripheral Port     No No Yes
Functional Safety Support          
Security TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller Optional Integrated GIC v1 (MP only) Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GICv2 External GICv2
Generic Timer No Yes Yes Armv8-A Armv8-A

Cortex-A Comparison Table (Armv8-A)

Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 Cortex-A65 Cortex-A65AE Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A76AE
Instruction set architecture and extensions Armv8-A AArch32 only Armv8-A AArch64 only Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only) Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A Armv8-A Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product Armv8-A, Armv8.1 extensions, Armv8.2 extensions, Cryptography extensions, RAS extensions, Armv8.3 (LDAPR instructions only), Armv8.4 Dot Product
Pipeline In order In order In order In order In order Out of order Out of order Out-of-order Out of order Out of order Out-of-order Out-of-order Out-of-order
Superscalar       Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Neon and Floating Point Unit Optional Optional Optional Optional Optional Included Included Included Included Included Included Included Included
Floating Point Unit only N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included
Cryptography Unit Optional Optional Optional Optional N/A Optional Optional Optional Optional Optional Optional Optional Optional
Physical Addressing (PA) 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 40-bit 40-bit 44-bit 40-bit 40-bit
Dual Core Lock-Step (DCLS) No No No No No No No Yes (in safety-mode) No No No No Yes (in safety-mode)
L1 I-Cache / D-Cache 8k-64k 8k-64k 8k-64k 8k-64k 16kB-64kB 48kB/32kB 16KB to 64KB 16KB to 64KB 48KB/32kB-64kB 32k/32k-64k 64KB 64KB 64KB
L2 Cache 128KB-1MB 128KB-1MB 128KB-1MB 128KB-2MB 64kB-256kB 512kB-2MB 64KB to 256KB 64KB to 256KB 512kB-4MB 256k-8MB 256KB to 512KB 256KB to 512KB 256KB to 512KB
L3 Cache NA NA NA NA Optional
From 256kB to 4MB
NA Optional 512KB to 4MB Optional 512KB to 4MB NA NA Optional 512KB to 4MB Optional 512KB to 4MB Optional 512KB to 4MB
ECC / Parity Yes Yes Yes Yes Yes Yes Yes Yes Yes L2 only Yes Yes Yes
LPAE Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Bus Interfaces ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI
ACP Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional
Peripheral Port         Optional   Optional Optional     Optional Optional Optional
Functional Safety Support Yes Yes Yes Yes Yes Yes   Yes Yes   Yes Yes Yes
Security TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone TrustZone
Interrupt Controller External
GICv3
External
GICv3
External
GICv3
External
GICv3
External
GICv4
External
GICv3
External
GICv4
External
GICv4
External
GICv3
External
GICv3
External
GICv4
External
GICv4
External
GICv4
Generic Timer Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A

 

Get Support

Arm support

Arm training courses and on-site system-design advisory services enable licensees to efficiently integrate the Cortex-A55 processor into their design to realize maximum system performance with lowest risk and fastest time-to-market.

Arm training courses  Arm Design Reviews  Open a support case

Community Blogs

Community Forums

Not answered What is the "Integer divide unit with support for operand-dependent early termination"? 0 votes 31 views 0 replies Started yesterday by jing Answer this
Answered Binary Semaphore upset by FIQ
  • Cortex-A
0 votes 822 views 20 replies Latest 3 days ago by 42Bastian Schick Answer this
Not answered Identifying Generic IP Components on an Access Port 0 votes 49 views 0 replies Started 3 days ago by Torsten Robitzki Answer this
Not answered Issue with WatchDog reset De-asserting 0 votes 56 views 0 replies Started 3 days ago by BAB Answer this
Not answered Getting processor and cache details
  • cache
  • Linux
0 votes 110 views 0 replies Started 6 days ago by karthikeyan.d Answer this
Not answered Loading cortex M1 soft processor on Pynq Processor
  • Cortex-M1
  • Cortex-M
0 votes 82 views 0 replies Started 6 days ago by Sivasankar Answer this
Not answered What is the "Integer divide unit with support for operand-dependent early termination"? Started yesterday by jing 0 replies 31 views
Answered Binary Semaphore upset by FIQ Latest 3 days ago by 42Bastian Schick 20 replies 822 views
Not answered Identifying Generic IP Components on an Access Port Started 3 days ago by Torsten Robitzki 0 replies 49 views
Not answered Issue with WatchDog reset De-asserting Started 3 days ago by BAB 0 replies 56 views
Not answered Getting processor and cache details Started 6 days ago by karthikeyan.d 0 replies 110 views
Not answered Loading cortex M1 soft processor on Pynq Processor Started 6 days ago by Sivasankar 0 replies 82 views