A highly power efficient mid-range application CPU built on Arm DynamIQ technology.
The Arm Cortex-A55 processor is a market-leading CPU that delivers the best combination of power efficiency and performance in its class. It is part of the first generation of application CPUs based on DynamIQ technology and features the latest Armv8-A architecture extensions, with dedicated machine learning instructions.
The Cortex-A55 incorporates an extensively redesigned microarchitecture system that improves performance across the board while being very competitive in area and power efficiency. It delivers up to 18% more performance at 15% better power efficiency when compared to its predecessor, the Cortex-A53.
Designed to be an extremely scalable CPU, the versatile Cortex-A55 can be used to address a wide range of applications with diverging cost, from the edge to the cloud. The Cortex-A55 can be implemented in both stand-alone applications or as a ‘LITTLE’ CPU to the Cortex-A7x series with DynamIQ big.LITTLE.
Arm Cortex-A55 CPU
Armv8.3 (LDAPR instructions only)
||A64, A32, and T32 instruction sets
|Neon / Floating Point Unit||Optional|
|Max Number of CPUs in Cluster||Eight (8)|
|Physical Addressing (PA)||40-bit|
|Memory System and External Interfaces||L1 I-Cache / D-Cache||16KB to 64KB
|L2 Cache||Optional, 64KB to 256KB|
|L3 Cache||Optional, 512KB to 4MB|
|Bus Interfaces||ACE or CHI|
|Other||Functional Safety Support||ASIL D systematic|
|Interrupts||GIC Interface, GICv4|
|Debug||Armv8-A (plus Armv8.2-A extensions)|
|Embedded Trace Macrocell||ETMv4.2 (instruction trace)
Featuring an extensive microarchitecture redesign, the Cortex-A55 processor is able to achieve breakthrough performance, while maintaining similar levels of power and 15% better power efficiency than the Cortex-A53. The efficiency gain enables the Cortex-A55 to deliver higher sustained performance for thermally constrained applications as well as exceptional power savings for low-power applications.
The Cortex-A55 features an integrated, configurable L2 cache within each CPU that achieves more than 50% reduced latency for memory accesses. It contains an L3 cache that is shared across up to eight Cortex-A55 CPUs within a single cluster. This new memory subsystem, which is designed for high bandwidth, improves overall compute performance while also reducing system power.
With support for the Armv8-A architecture, the Cortex-A55 processor is backwards-compatible with existing software and comes with a wealth of existing ecosystem support, from tools to Operating Systems. It also features the latest architecture extensions that introduce new NEON instructions for machine learning, advanced safety features and more support for Reliability, Accessibility and Serviceability (RAS).
The Cortex-A55 processor is designed to be compatible with the Cortex-A75 CPU for DynamIQ big.LITTLE, the next generation in big.LITTLE technology. DynamIQ big.LITTLE offers support for new CPU configurations, such as 1xbig + 7xLITTLE and 1xbig + 3xLITTLE, that achieve superior area efficiency, while delivering exceedingly high performance for richer, immersive experiences on all touchscreen-based devices.
Cortex-A comparison table for Armv7-A and Armv8-A
Download the following PDF datasheet to compare the specifications of Cortex-A Armv7-A and Armv8-A processors.